misc: Merge branch 'release-staging-v20.0.0.0' into develop

[gem5.git] / src / arch / riscv / bare_metal / fs_workload.hh

diff --git a/src/arch/riscv/bare_metal/fs_workload.hh b/src/arch/riscv/bare_metal/fs_workload.hh
index 722806d22b2be26cd0c5ef0ec423209ec52d09de..a142d47594bc22cbed8d77cc94133b9a510d7729 100644 (file)
--- a/src/arch/riscv/bare_metal/fs_workload.hh
+++ b/src/arch/riscv/bare_metal/fs_workload.hh
@@ -38,8 +38,8 @@ namespace RiscvISA
 class BareMetal : public RiscvISA::FsWorkload
 {
   protected:
-    ObjectFile *bootloader;
-    SymbolTable *bootloaderSymtab;
+    Loader::ObjectFile *bootloader;
+    Loader::SymbolTable *bootloaderSymtab;
 
   public:
     typedef RiscvBareMetalParams Params;
@@ -47,6 +47,18 @@ class BareMetal : public RiscvISA::FsWorkload
     ~BareMetal();
 
     void initState() override;
+
+    Loader::Arch getArch() const override { return bootloader->getArch(); }
+    const Loader::SymbolTable *
+    symtab(ThreadContext *tc) override
+    {
+        return bootloaderSymtab;
+    }
+    bool
+    insertSymbol(const Loader::Symbol &symbol) override
+    {
+        return bootloaderSymtab->insert(symbol);
+    }
 };
 
 } // namespace RiscvISA