#include "arch/riscv/utility.hh"
#include "cpu/static_inst.hh"
-using namespace std;
-
namespace RiscvISA
{
-string
+std::string
RegOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
- stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[0]);
- if (_srcRegIdx[1].index() != 0)
- ss << ", " << registerName(_srcRegIdx[1]);
- if (_srcRegIdx[2].index() != 0)
- ss << ", " << registerName(_srcRegIdx[2]);
+ std::stringstream ss;
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(0));
+ if (_numSrcRegs >= 2)
+ ss << ", " << registerName(srcRegIdx(1));
+ if (_numSrcRegs >= 3)
+ ss << ", " << registerName(srcRegIdx(2));
return ss.str();
}
-string
+std::string
CSROp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
- stringstream ss;
- ss << mnemonic << ' ' << registerName(_destRegIdx[0]) << ", ";
- if (_numSrcRegs > 0)
- ss << registerName(_srcRegIdx[0]) << ", ";
+ std::stringstream ss;
+ ss << mnemonic << ' ' << registerName(destRegIdx(0)) << ", ";
auto data = CSRData.find(csr);
if (data != CSRData.end())
ss << data->second.name;
else
- ss << "?? (" << hex << "0x" << csr << ")";
+ ss << "?? (" << std::hex << "0x" << csr << std::dec << ")";
+ if (_numSrcRegs > 0)
+ ss << ", " << registerName(srcRegIdx(0));
+ else
+ ss << uimm;
return ss.str();
}
-string
+std::string
SystemOp::generateDisassembly(Addr pc, const Loader::SymbolTable *symtab) const
{
if (strcmp(mnemonic, "fence_vma") == 0) {
- stringstream ss;
- ss << mnemonic << ' ' << registerName(_srcRegIdx[0]) << ", " <<
- registerName(_srcRegIdx[1]);
+ std::stringstream ss;
+ ss << mnemonic << ' ' << registerName(srcRegIdx(0)) << ", " <<
+ registerName(srcRegIdx(1));
return ss.str();
}