arch-riscv: Stop "using namespace std"

[gem5.git] / src / arch / riscv / isa / includes.isa

diff --git a/src/arch/riscv/isa/includes.isa b/src/arch/riscv/isa/includes.isa
index dfd0f37b427466e2d05b6d5d0664319ae1373d0a..d77d68e442931fc7e0458a806eeae0e62ed9916c 100644 (file)
--- a/src/arch/riscv/isa/includes.isa
+++ b/src/arch/riscv/isa/includes.isa
@@ -2,6 +2,7 @@
 
 // Copyright (c) 2015 RISC-V Foundation
 // Copyright (c) 2016 The University of Virginia
+// Copyright (c) 2020 Barkhausen Institut
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -26,9 +27,6 @@
 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-// Authors: Maxwell Walter
-//          Alec Roelke
 
 ////////////////////////////////////////////////////////////////////
 //
@@ -42,8 +40,13 @@ output header {{
 #include <tuple>
 #include <vector>
 
+#include "arch/riscv/insts/amo.hh"
+#include "arch/riscv/insts/compressed.hh"
+#include "arch/riscv/insts/mem.hh"
+#include "arch/riscv/insts/pseudo.hh"
 #include "arch/riscv/insts/standard.hh"
 #include "arch/riscv/insts/static_inst.hh"
+#include "arch/riscv/insts/unknown.hh"
 #include "cpu/static_inst.hh"
 #include "mem/packet.hh"
 #include "mem/request.hh"
@@ -58,7 +61,7 @@ output decoder {{
 
 #include "arch/riscv/decoder.hh"
 #include "arch/riscv/faults.hh"
-#include "arch/riscv/tlb.hh"
+#include "arch/riscv/mmu.hh"
 #include "base/cprintf.hh"
 #include "base/loader/symtab.hh"
 #include "cpu/thread_context.hh"
@@ -67,7 +70,6 @@ output decoder {{
 #include "sim/full_system.hh"
 
 using namespace RiscvISA;
-using namespace std;
 }};
 
 output exec {{
@@ -78,20 +80,22 @@ output exec {{
 
 #include "arch/generic/memhelpers.hh"
 #include "arch/riscv/faults.hh"
+#include "arch/riscv/mmu.hh"
 #include "arch/riscv/registers.hh"
 #include "arch/riscv/utility.hh"
 #include "base/condcodes.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
+#include "debug/RiscvMisc.hh"
 #include "mem/packet.hh"
 #include "mem/packet_access.hh"
 #include "mem/request.hh"
 #include "sim/eventq.hh"
 #include "sim/full_system.hh"
+#include "sim/pseudo_inst.hh"
 #include "sim/sim_events.hh"
 #include "sim/sim_exit.hh"
 #include "sim/system.hh"
 
 using namespace RiscvISA;
-using namespace std;
 }};