arch,cpu: Add a setThreadContext method to the ISA class.

[gem5.git] / src / arch / riscv / isa.cc

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index 055c95b35225b60b2cbc84d2805fcd28b4dba047..87c4043a4d83309784d17c14cd835e6bd268ff43 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -243,7 +243,7 @@ ISA::readMiscRegNoEffect(int misc_reg) const
 }
 
 RegVal
-ISA::readMiscReg(int misc_reg, ThreadContext *tc)
+ISA::readMiscReg(int misc_reg)
 {
     switch (misc_reg) {
       case MISCREG_HARTID:
@@ -330,7 +330,7 @@ ISA::setMiscRegNoEffect(int misc_reg, RegVal val)
 }
 
 void
-ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
+ISA::setMiscReg(int misc_reg, RegVal val)
 {
     if (misc_reg >= MISCREG_CYCLE && misc_reg <= MISCREG_HPMCOUNTER31) {
         // Ignore writes to HPM counters for now