arch-riscv: report that we don't have debugging support.

[gem5.git] / src / arch / riscv / isa.cc

diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc
index b6137fe9f5bf45d4eb7ce0009f7e19c82e10b1d3..ac26230a13cf9b2b09feb5f30a0109c36587a628 100644 (file)
--- a/src/arch/riscv/isa.cc
+++ b/src/arch/riscv/isa.cc
@@ -200,6 +200,9 @@ void ISA::clear()
                                   (1ULL << FS_OFFSET);
     miscRegFile[MISCREG_MCOUNTEREN] = 0x7;
     miscRegFile[MISCREG_SCOUNTEREN] = 0x7;
+    // don't set it to zero; software may try to determine the supported
+    // triggers, starting at zero. simply set a different value here.
+    miscRegFile[MISCREG_TSELECT] = 1;
 }
 
 bool
@@ -359,6 +362,13 @@ ISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc)
                 setMiscRegNoEffect(misc_reg, new_val);
             }
             break;
+          case MISCREG_TSELECT:
+            {
+                // we don't support debugging, so always set a different value
+                // than written
+                setMiscRegNoEffect(misc_reg, val + 1);
+            }
+            break;
           case MISCREG_ISA:
             {
                 auto cur_val = readMiscRegNoEffect(misc_reg);