arch-riscv: Add an implementation of set_tid_address syscall in RISCV

[gem5.git] / src / arch / riscv / process.hh

diff --git a/src/arch/riscv/process.hh b/src/arch/riscv/process.hh
index 8275a118a89db0e733967e02944787a561952f0b..2a27f350eb945768491e9df67acf259d4ed10c7a 100644 (file)
--- a/src/arch/riscv/process.hh
+++ b/src/arch/riscv/process.hh
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2006 The Regents of The University of Michigan
+ * Copyright (c) 2017 The University of Virginia
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -27,6 +28,7 @@
  *
  * Authors: Gabe Black
  *          Ali Saidi
+ *          Alec Roelke
  */
 
 #ifndef __RISCV_PROCESS_HH__
@@ -46,17 +48,21 @@ class RiscvProcess : public Process
   protected:
     RiscvProcess(ProcessParams * params, ObjectFile *objFile);
 
-    void initState();
+    void initState() override;
 
     template<class IntType>
     void argsInit(int pageSize);
 
   public:
-    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RiscvISA::IntReg getSyscallArg(ThreadContext *tc, int &i) override;
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
-    void setSyscallArg(ThreadContext *tc, int i, RiscvISA::IntReg val);
-    void setSyscallReturn(ThreadContext *tc, SyscallReturn return_value);
+    void setSyscallArg(ThreadContext *tc, int i,
+                       RiscvISA::IntReg val) override;
+    void setSyscallReturn(ThreadContext *tc,
+                          SyscallReturn return_value) override;
+
+    virtual bool mmapGrowsDown() const override { return false; }
 };
 
 /* No architectural page table defined for this ISA */