arch-riscv: implement RemoteGDB::acc for FS mode.

[gem5.git] / src / arch / riscv / remote_gdb.cc

diff --git a/src/arch/riscv/remote_gdb.cc b/src/arch/riscv/remote_gdb.cc
index f4e606e275af1f9f2306dd3ae5d3068a7cec367f..7da666d2eabbb31f3e55937063e381899ea6c5f9 100644 (file)
--- a/src/arch/riscv/remote_gdb.cc
+++ b/src/arch/riscv/remote_gdb.cc
@@ -2,6 +2,7 @@
  * Copyright 2015 LabWare
  * Copyright 2014 Google, Inc.
  * Copyright (c) 2010 ARM Limited
+ * Copyright (c) 2020 Barkhausen Institut
  * All rights reserved
  *
  * The license below extends only to copyright in the software and shall
@@ -39,12 +40,6 @@
  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Nathan Binkert
- *          William Wang
- *          Deyuan Guo
- *          Boris Shingarov
- *          Alec Roelke
  */
 
 /*
@@ -139,7 +134,9 @@
 
 #include <string>
 
+#include "arch/riscv/pagetable_walker.hh"
 #include "arch/riscv/registers.hh"
+#include "arch/riscv/tlb.hh"
 #include "cpu/thread_state.hh"
 #include "debug/GDBAcc.hh"
 #include "mem/page_table.hh"
@@ -156,7 +153,25 @@ RemoteGDB::RemoteGDB(System *_system, ThreadContext *tc, int _port)
 bool
 RemoteGDB::acc(Addr va, size_t len)
 {
-    panic_if(FullSystem, "acc not implemented for RISCV FS!");
+    if (FullSystem)
+    {
+        TLB *tlb = dynamic_cast<TLB *>(context()->getDTBPtr());
+        unsigned logBytes;
+        Addr paddr = va;
+
+        PrivilegeMode pmode = tlb->getMemPriv(context(), BaseTLB::Read);
+        SATP satp = context()->readMiscReg(MISCREG_SATP);
+        if (pmode != PrivilegeMode::PRV_M &&
+            satp.mode != AddrXlateMode::BARE) {
+            Walker *walker = tlb->getWalker();
+            Fault fault = walker->startFunctional(
+                    context(), paddr, logBytes, BaseTLB::Read);
+            if (fault != NoFault)
+                return false;
+        }
+        return true;
+    }
+
     return context()->getProcessPtr()->pTable->lookup(va) != nullptr;
 }
 
@@ -167,15 +182,6 @@ RemoteGDB::RiscvGdbRegCache::getRegs(ThreadContext *context)
     for (int i = 0; i < NumIntArchRegs; i++)
         r.gpr[i] = context->readIntReg(i);
     r.pc = context->pcState().pc();
-    for (int i = 0; i < NumFloatRegs; i++)
-        r.fpr[i] = context->readFloatRegBits(i);
-
-    r.csr_base = context->readMiscReg(0);
-    r.fflags = context->readMiscReg(MISCREG_FFLAGS);
-    r.frm = context->readMiscReg(MISCREG_FRM);
-    r.fcsr = context->readMiscReg(MISCREG_FCSR);
-    for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-        r.csr[i - ExplicitCSRs] = context->readMiscReg(i);
 }
 
 void
@@ -185,15 +191,6 @@ RemoteGDB::RiscvGdbRegCache::setRegs(ThreadContext *context) const
     for (int i = 0; i < NumIntArchRegs; i++)
         context->setIntReg(i, r.gpr[i]);
     context->pcState(r.pc);
-    for (int i = 0; i < NumFloatRegs; i++)
-        context->setFloatRegBits(i, r.fpr[i]);
-
-    context->setMiscReg(0, r.csr_base);
-    context->setMiscReg(MISCREG_FFLAGS, r.fflags);
-    context->setMiscReg(MISCREG_FRM, r.frm);
-    context->setMiscReg(MISCREG_FCSR, r.fcsr);
-    for (int i = ExplicitCSRs; i < NumMiscRegs; i++)
-        context->setMiscReg(i, r.csr[i - ExplicitCSRs]);
 }
 
 BaseGdbRegCache*