Automated merge with ssh://m5sim.org//repo/m5

[gem5.git] / src / arch / sparc / SConscript

diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index 81e96a8d6ec118af521f592f3cec291e9f57615f..126587835944149431c850e4b052f2defc9b541e 100644 (file)
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -32,6 +32,10 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'sparc':
+# Workaround for bug in SCons version > 0.97d20071212
+# Scons bug id: 2006 M5 Bug id: 308 
+    Dir('isa/formats')
+    Dir('isa/formats/mem')
     Source('asi.cc')
     Source('faults.cc')
     Source('floatregfile.cc')
@@ -44,10 +48,13 @@ if env['TARGET_ISA'] == 'sparc':
     Source('utility.cc')
 
     SimObject('SparcTLB.py')
+    TraceFlag('Sparc')
 
     if env['FULL_SYSTEM']:
         SimObject('SparcSystem.py')
+        SimObject('SparcInterrupts.py')
 
+        Source('interrupts.cc')
         Source('stacktrace.cc')
         Source('system.cc')
         Source('ua2005.cc')