Automated merge with ssh://m5sim.org//repo/m5

[gem5.git] / src / arch / sparc / SConscript

diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript
index e342c79cf8795b7cb77647a5077c448ed196e755..126587835944149431c850e4b052f2defc9b541e 100644 (file)
--- a/src/arch/sparc/SConscript
+++ b/src/arch/sparc/SConscript
@@ -32,20 +32,31 @@
 Import('*')
 
 if env['TARGET_ISA'] == 'sparc':
+# Workaround for bug in SCons version > 0.97d20071212
+# Scons bug id: 2006 M5 Bug id: 308 
+    Dir('isa/formats')
+    Dir('isa/formats/mem')
     Source('asi.cc')
     Source('faults.cc')
     Source('floatregfile.cc')
     Source('intregfile.cc')
     Source('miscregfile.cc')
+    Source('pagetable.cc')
     Source('regfile.cc')
     Source('remote_gdb.cc')
+    Source('tlb.cc')
+    Source('utility.cc')
+
+    SimObject('SparcTLB.py')
+    TraceFlag('Sparc')
 
     if env['FULL_SYSTEM']:
-        Source('arguments.cc')
-        Source('pagetable.cc')
+        SimObject('SparcSystem.py')
+        SimObject('SparcInterrupts.py')
+
+        Source('interrupts.cc')
         Source('stacktrace.cc')
         Source('system.cc')
-        Source('tlb.cc')
         Source('ua2005.cc')
         Source('vtophys.cc')
     else: