arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / decoder.hh

diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index 0386bd095ff8ab6ce785a1aec5489276805442fd..6fa506f37a65d200fb92717c8018e3235295aeaa 100644 (file)
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -31,13 +31,100 @@
 #ifndef __ARCH_SPARC_DECODER_HH__
 #define __ARCH_SPARC_DECODER_HH__
 
-#include "arch/generic/decoder.hh"
+#include "arch/generic/decode_cache.hh"
+#include "arch/sparc/registers.hh"
+#include "arch/types.hh"
+#include "cpu/static_inst.hh"
 
 namespace SparcISA
 {
 
-class Decoder : public GenericISA::Decoder
-{};
+class ISA;
+class Decoder
+{
+  protected:
+    // The extended machine instruction being generated
+    ExtMachInst emi;
+    bool instDone;
+    RegVal asi;
+
+  public:
+    Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
+    {}
+
+    void process() {}
+
+    void
+    reset()
+    {
+        instDone = false;
+    }
+
+    // Use this to give data to the predecoder. This should be used
+    // when there is control flow.
+    void
+    moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
+    {
+        emi = inst;
+        // The I bit, bit 13, is used to figure out where the ASI
+        // should come from. Use that in the ExtMachInst. This is
+        // slightly redundant, but it removes the need to put a condition
+        // into all the execute functions
+        if (inst & (1 << 13)) {
+            emi |= (static_cast<ExtMachInst>(
+                        asi << (sizeof(MachInst) * 8)));
+        } else {
+            emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
+                    << (sizeof(MachInst) * 8));
+        }
+        instDone = true;
+    }
+
+    bool
+    needMoreBytes()
+    {
+        return true;
+    }
+
+    bool
+    instReady()
+    {
+        return instDone;
+    }
+
+    void
+    setContext(RegVal _asi)
+    {
+        asi = _asi;
+    }
+
+    void takeOverFrom(Decoder *old) {}
+
+  protected:
+    /// A cache of decoded instruction objects.
+    static GenericISA::BasicDecodeCache defaultCache;
+
+  public:
+    StaticInstPtr decodeInst(ExtMachInst mach_inst);
+
+    /// Decode a machine instruction.
+    /// @param mach_inst The binary instruction to decode.
+    /// @retval A pointer to the corresponding StaticInst object.
+    StaticInstPtr
+    decode(ExtMachInst mach_inst, Addr addr)
+    {
+        return defaultCache.decode(this, mach_inst, addr);
+    }
+
+    StaticInstPtr
+    decode(SparcISA::PCState &nextPC)
+    {
+        if (!instDone)
+            return NULL;
+        instDone = false;
+        return decode(emi, nextPC.instAddr());
+    }
+};
 
 } // namespace SparcISA