arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / decoder.hh

diff --git a/src/arch/sparc/decoder.hh b/src/arch/sparc/decoder.hh
index ea079328664f784c4f712c2210254125ea112ca5..6fa506f37a65d200fb92717c8018e3235295aeaa 100644 (file)
--- a/src/arch/sparc/decoder.hh
+++ b/src/arch/sparc/decoder.hh
@@ -35,37 +35,23 @@
 #include "arch/sparc/registers.hh"
 #include "arch/types.hh"
 #include "cpu/static_inst.hh"
-#include "cpu/thread_context.hh"
-
-class ThreadContext;
 
 namespace SparcISA
 {
 
+class ISA;
 class Decoder
 {
   protected:
-    ThreadContext * tc;
     // The extended machine instruction being generated
     ExtMachInst emi;
     bool instDone;
+    RegVal asi;
 
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder(ISA* isa = nullptr) : instDone(false), asi(0)
     {}
 
-    ThreadContext *
-    getTC()
-    {
-        return tc;
-    }
-
-    void
-    setTC(ThreadContext * _tc)
-    {
-        tc = _tc;
-    }
-
     void process() {}
 
     void
@@ -86,8 +72,7 @@ class Decoder
         // into all the execute functions
         if (inst & (1 << 13)) {
             emi |= (static_cast<ExtMachInst>(
-                        tc->readMiscRegNoEffect(MISCREG_ASI))
-                    << (sizeof(MachInst) * 8));
+                        asi << (sizeof(MachInst) * 8)));
         } else {
             emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
                     << (sizeof(MachInst) * 8));
@@ -107,6 +92,14 @@ class Decoder
         return instDone;
     }
 
+    void
+    setContext(RegVal _asi)
+    {
+        asi = _asi;
+    }
+
+    void takeOverFrom(Decoder *old) {}
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;