* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Gabe Black
*/
#ifndef __ARCH_SPARC_INTERRUPT_HH__
#include "arch/sparc/faults.hh"
#include "cpu/thread_context.hh"
-
namespace SparcISA
{
- class Interrupts
- {
- protected:
+enum interrupts_t {
+ trap_level_zero,
+ hstick_match,
+ interrupt_vector,
+ cpu_mondo,
+ dev_mondo,
+ resumable_error,
+ soft_interrupt,
+ num_interrupt_types
+};
+
+class Interrupts
+{
+
+ private:
- public:
- Interrupts()
- {
+ bool interrupts[num_interrupt_types];
+ int numPosted;
+ public:
+ Interrupts()
+ {
+ for (int i = 0; i < num_interrupt_types; ++i) {
+ interrupts[i] = false;
}
- void post(int int_num, int index)
- {
+ numPosted = 0;
+ }
+ void post(int int_type)
+ {
+ if (int_type < 0 || int_type >= num_interrupt_types)
+ panic("posting unknown interrupt!\n");
+ if (interrupts[int_type] == false) {
+ interrupts[int_type] = true;
+ ++numPosted;
}
+ }
- void clear(int int_num, int index)
- {
+ void post(int int_num, int index)
+ {
- }
+ }
- void clear_all()
- {
+ void clear(int int_num, int index)
+ {
- }
+ }
- bool check_interrupts(ThreadContext * tc) const
- {
- // so far only handle softint interrupts
- int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
- if (int_level)
- return true;
- else
- return false;
- }
+ void clear_all()
+ {
+
+ }
- Fault getInterrupt(ThreadContext * tc)
- {
- // conditioning the softint interrups
- if (tc->readMiscReg(MISCREG_HPSTATE) & hpriv) {
- // if running in privileged mode, then pend the interrupt
- return NoFault;
+ bool check_interrupts(ThreadContext * tc) const
+ {
+ if (numPosted)
+ return true;
+ else
+ return false;
+ }
+
+ Fault getInterrupt(ThreadContext * tc)
+ {
+ int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
+ int pstate = tc->readMiscReg(MISCREG_PSTATE);
+ bool ie = pstate & PSTATE::ie;
+
+ // THESE ARE IN ORDER OF PRIORITY
+ // since there are early returns, and the highest
+ // priority interrupts should get serviced,
+ // it is v. important that new interrupts are inserted
+ // in the right order of processing
+ if (hpstate & HPSTATE::hpriv) {
+ if (ie) {
+ if (interrupts[hstick_match]) {
+ if (tc->readMiscReg(MISCREG_HINTP) & 1) {
+ interrupts[hstick_match] = false;
+ --numPosted;
+ return new HstickMatch;
+ }
+ }
+ if (interrupts[interrupt_vector]) {
+ interrupts[interrupt_vector] = false;
+ --numPosted;
+ //HAVEN'T IMPLed THIS YET
+ return NoFault;
+ }
} else {
- int int_level = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
- if ((int_level <= tc->readMiscReg(MISCREG_PIL)) ||
- !(tc->readMiscReg(MISCREG_PSTATE) & ie)) {
- // if PIL or no interrupt enabled, then pend the interrupt
+ if (interrupts[hstick_match]) {
return NoFault;
- } else {
- return new InterruptLevelN(int_level);
+ }
+
+ }
+ } else {
+ if (interrupts[trap_level_zero]) {
+ if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
+ interrupts[trap_level_zero] = false;
+ --numPosted;
+ return new TrapLevelZero;
+ }
+ }
+ if (interrupts[hstick_match]) {
+ if (tc->readMiscReg(MISCREG_HINTP) & 1) {
+ interrupts[hstick_match] = false;
+ --numPosted;
+ return new HstickMatch;
+ }
+ }
+ if (ie) {
+ if (interrupts[cpu_mondo]) {
+ interrupts[cpu_mondo] = false;
+ --numPosted;
+ return new CpuMondo;
+ }
+ if (interrupts[dev_mondo]) {
+ interrupts[dev_mondo] = false;
+ --numPosted;
+ return new DevMondo;
+ }
+ if (interrupts[soft_interrupt]) {
+ int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
+ // it seems that interrupt vectors are right in
+ // the middle of interrupt levels with regard to
+ // priority, so have to check
+ if ((il < 6) &&
+ interrupts[interrupt_vector]) {
+ // may require more details here since there
+ // may be lots of interrupts embedded in an
+ // platform interrupt vector
+ interrupts[interrupt_vector] = false;
+ --numPosted;
+ //HAVEN'T IMPLed YET
+ return NoFault;
+ } else {
+ if (il > tc->readMiscReg(MISCREG_PIL)) {
+ uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
+ uint64_t more = si & ~(1 << (il + 1));
+ if (!InterruptLevel(more)) {
+ interrupts[soft_interrupt] = false;
+ --numPosted;
+ }
+ return new InterruptLevelN(il);
+ }
+ }
+ }
+ if (interrupts[resumable_error]) {
+ interrupts[resumable_error] = false;
+ --numPosted;
+ return new ResumableError;
}
}
}
+ return NoFault;
+ }
- void updateIntrInfo(ThreadContext * tc)
- {
+ void updateIntrInfo(ThreadContext * tc)
+ {
- }
+ }
- void serialize(std::ostream &os)
- {
- }
+ void serialize(std::ostream &os)
+ {
+ SERIALIZE_ARRAY(interrupts,num_interrupt_types);
+ SERIALIZE_SCALAR(numPosted);
+ }
- void unserialize(Checkpoint *cp, const std::string §ion)
- {
- }
- };
-}
+ void unserialize(Checkpoint *cp, const std::string §ion)
+ {
+ UNSERIALIZE_ARRAY(interrupts,num_interrupt_types);
+ UNSERIALIZE_SCALAR(numPosted);
+ }
+};
+} // namespace SPARC_ISA
#endif // __ARCH_SPARC_INTERRUPT_HH__
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