cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

[gem5.git] / src / arch / sparc / isa / formats / mem / basicmem.isa

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 1d9075a570f7cf0c6d18279e51aa931d81e31ee4..bc7d033b6c8bcbaa73d2c96878bc3832c70a73a0 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -1,4 +1,6 @@
-// Copyright (c) 2006 The Regents of The University of Michigan
+// -*- mode:c++ -*-
+
+// Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
 // Redistribution and use in source and binary forms, with or without
@@ -43,52 +45,54 @@ def template MemDeclare {{
             /// Constructor.
             %(class_name)s(ExtMachInst machInst);
 
-            %(BasicExecDeclare)s
-
-            %(InitiateAccDeclare)s
-
-            %(CompleteAccDeclare)s
+            Fault execute(ExecContext *, Trace::InstRecord *) const;
+            Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+            Fault completeAcc(PacketPtr, ExecContext *,
+                              Trace::InstRecord *) const;
         };
 }};
 
 let {{
-    def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags):
+    def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
         addrCalcReg = 'EA = Rs1 + Rs2;'
         addrCalcImm = 'EA = Rs1 + imm;'
         iop = InstObjParams(name, Name, 'Mem',
-                {"code": code, "fault_check": faultCode,
-                 "ea_code": addrCalcReg},
-                opt_flags)
+                {"code": code, "postacc_code" : postacc_code,
+                 "fault_check": faultCode, "ea_code": addrCalcReg,
+                 "EA_trunc": TruncateEA}, opt_flags)
         iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
-                {"code": code, "fault_check": faultCode,
-                 "ea_code": addrCalcImm},
-                opt_flags)
+                {"code": code, "postacc_code" : postacc_code,
+                 "fault_check": faultCode, "ea_code": addrCalcImm,
+                 "EA_trunc": TruncateEA}, opt_flags)
         header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
         decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
         decode_block = ROrImmDecode.subst(iop)
-        exec_output = doDualSplitExecute(code, addrCalcReg, addrCalcImm,
-                execute, faultCode, name, name + "Imm",
+        exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
+                addrCalcImm, execute, faultCode, name, name + "Imm",
                 Name, Name + "Imm", asi, opt_flags)
         return (header_output, decoder_output, exec_output, decode_block)
 }};
 
-def format LoadAlt(code, asi, *opt_flags) {{
+def format LoadAlt(code, *opt_flags) {{
+        code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, LoadFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
-def format StoreAlt(code, asi, *opt_flags) {{
+def format StoreAlt(code, *opt_flags) {{
+        code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code, StoreFuncs,
-            AlternateASIPrivFaultCheck, name, Name, asi, opt_flags)
+            AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
 }};
 
 def format Load(code, *opt_flags) {{
+        code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
@@ -97,9 +101,30 @@ def format Load(code, *opt_flags) {{
 }};
 
 def format Store(code, *opt_flags) {{
+        code = filterDoubles(code)
         (header_output,
          decoder_output,
          exec_output,
          decode_block) = doMemFormat(code,
              StoreFuncs, '', name, Name, 0, opt_flags)
 }};
+
+def format StoreFsr(code, *opt_flags) {{
+        code = filterDoubles(code)
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code,
+             StoreFuncs, '', name, Name, 0, opt_flags,
+             'Fsr = insertBits(Fsr,16,14,0);')
+}};
+
+def format TwinLoad(code, *opt_flags) {{
+        (header_output,
+         decoder_output,
+         exec_output,
+         decode_block) = doMemFormat(code, LoadFuncs,
+            AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
+            name, Name, "EXT_ASI", opt_flags)
+}};
+