cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

[gem5.git] / src / arch / sparc / isa / formats / mem / basicmem.isa

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 5dcb955e364cd3e4feb93086a17c797e3c082682..bc7d033b6c8bcbaa73d2c96878bc3832c70a73a0 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -45,13 +45,10 @@ def template MemDeclare {{
             /// Constructor.
             %(class_name)s(ExtMachInst machInst);
 
-            %(BasicExecDeclare)s
-
-            %(EACompDeclare)s
-
-            %(InitiateAccDeclare)s
-
-            %(CompleteAccDeclare)s
+            Fault execute(ExecContext *, Trace::InstRecord *) const;
+            Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+            Fault completeAcc(PacketPtr, ExecContext *,
+                              Trace::InstRecord *) const;
         };
 }};
 
@@ -73,8 +70,6 @@ let {{
         exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
                 addrCalcImm, execute, faultCode, name, name + "Imm",
                 Name, Name + "Imm", asi, opt_flags)
-        exec_output +=  EACompExecute.subst(iop);
-        exec_output +=  EACompExecute.subst(iop_imm);
         return (header_output, decoder_output, exec_output, decode_block)
 }};