cpu,alpha,mips,power,riscv,sparc: Get rid of eaComp and memAccInst.

[gem5.git] / src / arch / sparc / isa / formats / mem / basicmem.isa

diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index c7bb3e435a8cac8d853d31b0acbc57562dba040d..bc7d033b6c8bcbaa73d2c96878bc3832c70a73a0 100644 (file)
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -1,3 +1,5 @@
+// -*- mode:c++ -*-
+
 // Copyright (c) 2006-2007 The Regents of The University of Michigan
 // All rights reserved.
 //
@@ -43,11 +45,10 @@ def template MemDeclare {{
             /// Constructor.
             %(class_name)s(ExtMachInst machInst);
 
-            %(BasicExecDeclare)s
-
-            %(InitiateAccDeclare)s
-
-            %(CompleteAccDeclare)s
+            Fault execute(ExecContext *, Trace::InstRecord *) const;
+            Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
+            Fault completeAcc(PacketPtr, ExecContext *,
+                              Trace::InstRecord *) const;
         };
 }};