#include "arch/sparc/registers.hh"
#include "arch/sparc/types.hh"
#include "cpu/cpuevent.hh"
+#include "cpu/reg_class.hh"
#include "sim/sim_object.hh"
class Checkpoint;
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
- void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
- MiscReg readFSReg(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, RegVal val, ThreadContext *tc);
+ RegVal readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
void clear();
- void serialize(EventManager *em, std::ostream & os);
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
- void unserialize(EventManager *em, Checkpoint *cp,
- const std::string & section);
+ void startup(ThreadContext *tc) {}
- protected:
+ /// Explicitly import the otherwise hidden startup
+ using SimObject::startup;
+ protected:
bool isHyperPriv() { return hpstate.hpriv; }
bool isPriv() { return hpstate.hpriv || pstate.priv; }
bool isNonPriv() { return !isPriv(); }
public:
- MiscReg readMiscRegNoEffect(int miscReg);
- MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+ RegVal readMiscRegNoEffect(int miscReg) const;
+ RegVal readMiscReg(int miscReg, ThreadContext *tc);
- void setMiscRegNoEffect(int miscReg, const MiscReg val);
- void setMiscReg(int miscReg, const MiscReg val,
- ThreadContext *tc);
+ void setMiscRegNoEffect(int miscReg, RegVal val);
+ void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+
+ RegId
+ flattenRegId(const RegId& regId) const
+ {
+ switch (regId.classValue()) {
+ case IntRegClass:
+ return RegId(IntRegClass, flattenIntIndex(regId.index()));
+ case FloatRegClass:
+ return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+ case CCRegClass:
+ return RegId(CCRegClass, flattenCCIndex(regId.index()));
+ case MiscRegClass:
+ return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+ default:
+ break;
+ }
+ return regId;
+ }
int
- flattenIntIndex(int reg)
+ flattenIntIndex(int reg) const
{
assert(reg < TotalInstIntRegs);
RegIndex flatIndex = intRegMap[reg];
}
int
- flattenFloatIndex(int reg)
+ flattenFloatIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenVecIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenVecElemIndex(int reg) const
{
return reg;
}
+ int
+ flattenVecPredIndex(int reg) const
+ {
+ return reg;
+ }
+
+ // dummy
+ int
+ flattenCCIndex(int reg) const
+ {
+ return reg;
+ }
+
+ int
+ flattenMiscIndex(int reg) const
+ {
+ return reg;
+ }
+
+
typedef SparcISAParams Params;
const Params *params() const;