arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / isa.hh

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index ded5b34ffdbe94462c04617b193b95aa03f296b4..6cda320380c6e087cf5429d8aee0c4e07533c820 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -116,8 +116,8 @@ class ISA : public SimObject
 
     // These need to check the int_dis field and if 0 then
     // set appropriate bit in softint and checkinterrutps on the cpu
-    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
-    MiscReg readFSReg(int miscReg, ThreadContext * tc);
+    void  setFSReg(int miscReg, RegVal val, ThreadContext *tc);
+    RegVal readFSReg(int miscReg, ThreadContext * tc);
 
     // Update interrupt state on softint or pil change
     void checkSoftInt(ThreadContext *tc);
@@ -183,12 +183,11 @@ class ISA : public SimObject
 
   public:
 
-    MiscReg readMiscRegNoEffect(int miscReg) const;
-    MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+    RegVal readMiscRegNoEffect(int miscReg) const;
+    RegVal readMiscReg(int miscReg, ThreadContext *tc);
 
-    void setMiscRegNoEffect(int miscReg, const MiscReg val);
-    void setMiscReg(int miscReg, const MiscReg val,
-            ThreadContext *tc);
+    void setMiscRegNoEffect(int miscReg, RegVal val);
+    void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
 
     RegId
     flattenRegId(const RegId& regId) const
@@ -202,6 +201,8 @@ class ISA : public SimObject
             return RegId(CCRegClass, flattenCCIndex(regId.index()));
           case MiscRegClass:
             return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+          default:
+            break;
         }
         return regId;
     }
@@ -221,6 +222,24 @@ class ISA : public SimObject
         return reg;
     }
 
+    int
+    flattenVecIndex(int reg) const
+    {
+        return reg;
+    }
+
+    int
+    flattenVecElemIndex(int reg) const
+    {
+        return reg;
+    }
+
+    int
+    flattenVecPredIndex(int reg) const
+    {
+        return reg;
+    }
+
     // dummy
     int
     flattenCCIndex(int reg) const