arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / isa.hh

diff --git a/src/arch/sparc/isa.hh b/src/arch/sparc/isa.hh
index e5d2587863b3412dad42cd23eeda7ca3485c6d71..6cda320380c6e087cf5429d8aee0c4e07533c820 100644 (file)
--- a/src/arch/sparc/isa.hh
+++ b/src/arch/sparc/isa.hh
@@ -37,14 +37,17 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/types.hh"
 #include "cpu/cpuevent.hh"
+#include "cpu/reg_class.hh"
+#include "sim/sim_object.hh"
 
 class Checkpoint;
 class EventManager;
+struct SparcISAParams;
 class ThreadContext;
 
 namespace SparcISA
 {
-class ISA
+class ISA : public SimObject
 {
   private:
 
@@ -71,7 +74,7 @@ class ISA
                             // on the previous level)
     uint64_t tba;           // Trap Base Address
 
-    uint16_t pstate;        // Process State Register
+    PSTATE pstate;        // Process State Register
     uint8_t tl;             // Trap Level
     uint8_t pil;            // Process Interrupt Register
     uint8_t cwp;            // Current Window Pointer
@@ -83,7 +86,7 @@ class ISA
     uint8_t gl;             // Global level register
 
     /** Hyperprivileged Registers */
-    uint64_t hpstate;       // Hyperprivileged State Register
+    HPSTATE hpstate;       // Hyperprivileged State Register
     uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
     uint64_t hintp;
     uint64_t htba;          // Hyperprivileged Trap Base Address register
@@ -113,8 +116,8 @@ class ISA
 
     // These need to check the int_dis field and if 0 then
     // set appropriate bit in softint and checkinterrutps on the cpu
-    void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
-    MiscReg readFSReg(int miscReg, ThreadContext * tc);
+    void  setFSReg(int miscReg, RegVal val, ThreadContext *tc);
+    RegVal readFSReg(int miscReg, ThreadContext * tc);
 
     // Update interrupt state on softint or pil change
     void checkSoftInt(ThreadContext *tc);
@@ -165,28 +168,47 @@ class ISA
 
     void clear();
 
-    void serialize(EventManager *em, std::ostream & os);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
 
-    void unserialize(EventManager *em, Checkpoint *cp,
-                     const std::string & section);
+    void startup(ThreadContext *tc) {}
 
-  protected:
+    /// Explicitly import the otherwise hidden startup
+    using SimObject::startup;
 
-    bool isHyperPriv() { return (hpstate & (1 << 2)); }
-    bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
+  protected:
+    bool isHyperPriv() { return hpstate.hpriv; }
+    bool isPriv() { return hpstate.hpriv || pstate.priv; }
     bool isNonPriv() { return !isPriv(); }
 
   public:
 
-    MiscReg readMiscRegNoEffect(int miscReg);
-    MiscReg readMiscReg(int miscReg, ThreadContext *tc);
+    RegVal readMiscRegNoEffect(int miscReg) const;
+    RegVal readMiscReg(int miscReg, ThreadContext *tc);
 
-    void setMiscRegNoEffect(int miscReg, const MiscReg val);
-    void setMiscReg(int miscReg, const MiscReg val,
-            ThreadContext *tc);
+    void setMiscRegNoEffect(int miscReg, RegVal val);
+    void setMiscReg(int miscReg, RegVal val, ThreadContext *tc);
+
+    RegId
+    flattenRegId(const RegId& regId) const
+    {
+        switch (regId.classValue()) {
+          case IntRegClass:
+            return RegId(IntRegClass, flattenIntIndex(regId.index()));
+          case FloatRegClass:
+            return RegId(FloatRegClass, flattenFloatIndex(regId.index()));
+          case CCRegClass:
+            return RegId(CCRegClass, flattenCCIndex(regId.index()));
+          case MiscRegClass:
+            return RegId(MiscRegClass, flattenMiscIndex(regId.index()));
+          default:
+            break;
+        }
+        return regId;
+    }
 
     int
-    flattenIntIndex(int reg)
+    flattenIntIndex(int reg) const
     {
         assert(reg < TotalInstIntRegs);
         RegIndex flatIndex = intRegMap[reg];
@@ -195,19 +217,47 @@ class ISA
     }
 
     int
-    flattenFloatIndex(int reg)
+    flattenFloatIndex(int reg) const
     {
         return reg;
     }
 
-    ISA()
+    int
+    flattenVecIndex(int reg) const
     {
-        tickCompare = NULL;
-        sTickCompare = NULL;
-        hSTickCompare = NULL;
+        return reg;
+    }
 
-        clear();
+    int
+    flattenVecElemIndex(int reg) const
+    {
+        return reg;
     }
+
+    int
+    flattenVecPredIndex(int reg) const
+    {
+        return reg;
+    }
+
+    // dummy
+    int
+    flattenCCIndex(int reg) const
+    {
+        return reg;
+    }
+
+    int
+    flattenMiscIndex(int reg) const
+    {
+        return reg;
+    }
+
+
+    typedef SparcISAParams Params;
+    const Params *params() const;
+
+    ISA(Params *p);
 };
 }