X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / sparc / isa_traits.hh

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 109fdfae7d0fa067223d4e299014df53c95a9780..0a568ddbec1a8b7878eabc7f97fefa8ba923638b 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -33,23 +33,17 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "base/misc.hh"
+#include "arch/sparc/sparc_traits.hh"
+#include "base/types.hh"
 #include "config/full_system.hh"
-#include "sim/host.hh"
 
-class ThreadContext;
-class FastCPU;
-//class FullCPU;
-class Checkpoint;
-
-class StaticInst;
 class StaticInstPtr;
 
 namespace BigEndianGuest {}
 
 namespace SparcISA
 {
-    class RegFile;
+    const int MachineBytes = 8;
 
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
@@ -60,92 +54,24 @@ namespace SparcISA
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    const int NumRegularIntRegs = 32;
-    const int NumMicroIntRegs = 1;
-    const int NumIntRegs =
-        NumRegularIntRegs +
-        NumMicroIntRegs;
-    const int NumFloatRegs = 64;
-    const int NumMiscRegs = 40;
-
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        // 0..31 are the integer regs 0..31
-        // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = NumIntRegs,
-        Ctrl_Base_DepTag = NumIntRegs + NumMicroIntRegs + NumFloatRegs,
-    };
-
-
-    // MAXTL - maximum trap level
-    const int MaxPTL = 2;
-    const int MaxTL  = 6;
-    const int MaxGL  = 3;
-    const int MaxPGL = 2;
-
-    // NWINDOWS - number of register windows, can be 3 to 32
-    const int NWindows = 8;
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;     // architecturally meaningful
-    // the rest of these depend on the ABI
-    const int StackPointerReg = 14;
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
-    const int FramePointerReg = 30;
-    const int ArgumentReg0 = 8;
-    const int ArgumentReg1 = 9;
-    const int ArgumentReg2 = 10;
-    const int ArgumentReg3 = 11;
-    const int ArgumentReg4 = 12;
-    const int ArgumentReg5 = 13;
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = ArgumentReg1;
-
-    //XXX These numbers are bogus
-    const int MaxInstSrcRegs = 8;
-    const int MaxInstDestRegs = 9;
-
     //8K. This value is implmentation specific; and should probably
     //be somewhere else.
     const int LogVMPageSize = 13;
     const int VMPageSize = (1 << LogVMPageSize);
 
+    // real address virtual mapping
+    // sort of like alpha super page, but less frequently used
+    const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
+    const Addr SegKPMBase = ULL(0xfffffac000000000);
+
     //Why does both the previous set of constants and this one exist?
     const int PageShift = 13;
-    const int PageBytes = ULL(1) << PageShift;
+    const int PageBytes = 1ULL << PageShift;
 
     const int BranchPredAddrShiftAmt = 2;
 
-    const int MachineBytes = 8;
-    const int WordBytes = 4;
-    const int HalfwordBytes = 2;
-    const int ByteBytes = 1;
-
-    void serialize(std::ostream & os);
-
-    void unserialize(Checkpoint *cp, const std::string &section);
-
     StaticInstPtr decodeInst(ExtMachInst);
 
-    // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
-
-#if FULL_SYSTEM
-    ////////// Interrupt Stuff ///////////
-    enum InterruptLevels
-    {
-       INTLEVEL_MIN = 1,
-       INTLEVEL_MAX = 15,
-
-       NumInterruptLevels = INTLEVEL_MAX - INTLEVEL_MIN
-    };
-
-    // I don't know what it's for, so I don't
-    // know what SPARC's value should be
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
     /////////// TLB Stuff ////////////
     const Addr StartVAddrHole = ULL(0x0000800000000000);
     const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
@@ -153,7 +79,23 @@ namespace SparcISA
     const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
     const Addr BytesInPageMask = ULL(0x1FFF);
 
+#if FULL_SYSTEM
+    enum InterruptTypes
+    {
+        IT_TRAP_LEVEL_ZERO,
+        IT_HINTP,
+        IT_INT_VEC,
+        IT_CPU_MONDO,
+        IT_DEV_MONDO,
+        IT_RES_ERROR,
+        IT_SOFT_INT,
+        NumInterruptTypes
+    };
+
 #endif
+
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__