X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / sparc / isa_traits.hh

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 1c783a9b9a173f37f5dbd7b1b11ade0f6828a168..0a568ddbec1a8b7878eabc7f97fefa8ba923638b 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -33,10 +33,9 @@
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "arch/sparc/max_inst_regs.hh"
 #include "arch/sparc/sparc_traits.hh"
-#include "config/full_system.hh"
 #include "base/types.hh"
+#include "config/full_system.hh"
 
 class StaticInstPtr;
 
@@ -44,14 +43,10 @@ namespace BigEndianGuest {}
 
 namespace SparcISA
 {
-    class RegFile;
-
     const int MachineBytes = 8;
 
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
-    using SparcISAInst::MaxInstSrcRegs;
-    using SparcISAInst::MaxInstDestRegs;
 
     // SPARC has a delay slot
     #define ISA_HAS_DELAY_SLOT 1
@@ -59,23 +54,6 @@ namespace SparcISA
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        FP_Base_DepTag = 32*3+9,
-        Ctrl_Base_DepTag = FP_Base_DepTag + 64
-    };
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;      // architecturally meaningful
-    // the rest of these depend on the ABI
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8;  // Post return, 24 is pre-return.
-    const int StackPointerReg = 14;
-    const int FramePointerReg = 30;
-
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = 9;
-
     //8K. This value is implmentation specific; and should probably
     //be somewhere else.
     const int LogVMPageSize = 13;
@@ -102,11 +80,6 @@ namespace SparcISA
     const Addr BytesInPageMask = ULL(0x1FFF);
 
 #if FULL_SYSTEM
-    // I don't know what it's for, so I don't
-    // know what SPARC's value should be
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
     enum InterruptTypes
     {
         IT_TRAP_LEVEL_ZERO,
@@ -120,6 +93,9 @@ namespace SparcISA
     };
 
 #endif
+
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__