SPARC: Get rid of the setGlobals function.

[gem5.git] / src / arch / sparc / isa_traits.hh

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index fb09121a3128717737ba1a57d38534e774ba7d51..30455792fd04b0faf86bab2c42db9d3420608a06 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -26,112 +26,103 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  *
  * Authors: Gabe Black
+ *          Ali Saidi
  */
 
 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
 #include "arch/sparc/types.hh"
-#include "base/misc.hh"
+#include "arch/sparc/max_inst_regs.hh"
+#include "arch/sparc/sparc_traits.hh"
 #include "config/full_system.hh"
 #include "sim/host.hh"
 
-class ThreadContext;
-class FastCPU;
-//class FullCPU;
-class Checkpoint;
-
-class StaticInst;
 class StaticInstPtr;
 
 namespace BigEndianGuest {}
 
-#if FULL_SYSTEM
-#include "arch/sparc/isa_fullsys_traits.hh"
-#endif
-
 namespace SparcISA
 {
     class RegFile;
 
+    const int MachineBytes = 8;
+
     //This makes sure the big endian versions of certain functions are used.
     using namespace BigEndianGuest;
+    using SparcISAInst::MaxInstSrcRegs;
+    using SparcISAInst::MaxInstDestRegs;
 
-    // SPARC have a delay slot
+    // SPARC has a delay slot
     #define ISA_HAS_DELAY_SLOT 1
 
     // SPARC NOP (sethi %(hi(0), g0)
     const MachInst NoopMachInst = 0x01000000;
 
-    const int NumIntRegs = 32;
-    const int NumFloatRegs = 64;
-    const int NumMiscRegs = 40;
-
     // These enumerate all the registers for dependence tracking.
     enum DependenceTags {
-        // 0..31 are the integer regs 0..31
-        // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
-        FP_Base_DepTag = NumIntRegs,
-        Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
-        //XXX These are here solely to get compilation and won't work
-        Fpcr_DepTag = 0,
-        Uniq_DepTag = 0
+        FP_Base_DepTag = 32*3+9,
+        Ctrl_Base_DepTag = FP_Base_DepTag + 64
     };
 
-
-    // MAXTL - maximum trap level
-    const int MaxPTL = 2;
-    const int MaxTL  = 6;
-    const int MaxGL  = 3;
-    const int MaxPGL = 2;
-
-    // NWINDOWS - number of register windows, can be 3 to 32
-    const int NWindows = 8;
-
     // semantically meaningful register indices
-    const int ZeroReg = 0;     // architecturally meaningful
+    const int ZeroReg = 0;      // architecturally meaningful
     // the rest of these depend on the ABI
     const int StackPointerReg = 14;
     const int ReturnAddressReg = 31; // post call, precall is 15
     const int ReturnValueReg = 8; // Post return, 24 is pre-return.
     const int FramePointerReg = 30;
-    const int ArgumentReg0 = 8;
-    const int ArgumentReg1 = 9;
-    const int ArgumentReg2 = 10;
-    const int ArgumentReg3 = 11;
-    const int ArgumentReg4 = 12;
-    const int ArgumentReg5 = 13;
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = ArgumentReg1;
 
-    //XXX These numbers are bogus
-    const int MaxInstSrcRegs = 8;
-    const int MaxInstDestRegs = 9;
+    const int ArgumentReg[] = {8, 9, 10, 11, 12, 13};
+    const int NumArgumentRegs = sizeof(ArgumentReg) / sizeof(const int);
+
+    // Some OS syscall use a second register (o1) to return a second value
+    const int SyscallPseudoReturnReg = ArgumentReg[1];
 
     //8K. This value is implmentation specific; and should probably
     //be somewhere else.
     const int LogVMPageSize = 13;
     const int VMPageSize = (1 << LogVMPageSize);
 
+    // real address virtual mapping
+    // sort of like alpha super page, but less frequently used
+    const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
+    const Addr SegKPMBase = ULL(0xfffffac000000000);
+
     //Why does both the previous set of constants and this one exist?
     const int PageShift = 13;
-    const int PageBytes = ULL(1) << PageShift;
+    const int PageBytes = 1ULL << PageShift;
 
     const int BranchPredAddrShiftAmt = 2;
 
-    const int MachineBytes = 8;
-    const int WordBytes = 4;
-    const int HalfwordBytes = 2;
-    const int ByteBytes = 1;
-
-    void serialize(std::ostream & os);
+    StaticInstPtr decodeInst(ExtMachInst);
 
-    void unserialize(Checkpoint *cp, const std::string &section);
+    /////////// TLB Stuff ////////////
+    const Addr StartVAddrHole = ULL(0x0000800000000000);
+    const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+    const Addr VAddrAMask = ULL(0xFFFFFFFF);
+    const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+    const Addr BytesInPageMask = ULL(0x1FFF);
 
-    StaticInstPtr decodeInst(ExtMachInst);
+#if FULL_SYSTEM
+    // I don't know what it's for, so I don't
+    // know what SPARC's value should be
+    // For loading... XXX This maybe could be USegEnd?? --ali
+    const Addr LoadAddrMask = ULL(0xffffffffff);
+
+    enum InterruptTypes
+    {
+        IT_TRAP_LEVEL_ZERO,
+        IT_HINTP,
+        IT_INT_VEC,
+        IT_CPU_MONDO,
+        IT_DEV_MONDO,
+        IT_RES_ERROR,
+        IT_SOFT_INT,
+        NumInterruptTypes
+    };
 
-    // return a no-op instruction... used for instruction fetch faults
-    extern const MachInst NoopMachInst;
+#endif
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__