ISA: Back-out NoopMachInst as a StaticInstPtr change.

[gem5.git] / src / arch / sparc / isa_traits.hh

diff --git a/src/arch/sparc/isa_traits.hh b/src/arch/sparc/isa_traits.hh
index 8b3ec36a6b801156ff1d5f6ca2f37eca41cb0d06..9b02a4d80f619d7caebec08a1cb641e09ed18970 100644 (file)
--- a/src/arch/sparc/isa_traits.hh
+++ b/src/arch/sparc/isa_traits.hh
@@ -32,100 +32,65 @@
 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
 #define __ARCH_SPARC_ISA_TRAITS_HH__
 
-#include "arch/sparc/types.hh"
 #include "arch/sparc/sparc_traits.hh"
-#include "config/full_system.hh"
-#include "sim/host.hh"
-
-class StaticInstPtr;
+#include "arch/sparc/types.hh"
+#include "base/types.hh"
+#include "cpu/static_inst_fwd.hh"
 
 namespace BigEndianGuest {}
 
 namespace SparcISA
 {
-    class RegFile;
-
-    const int MachineBytes = 8;
-
-    //This makes sure the big endian versions of certain functions are used.
-    using namespace BigEndianGuest;
-
-    // SPARC has a delay slot
-    #define ISA_HAS_DELAY_SLOT 1
-
-    // SPARC NOP (sethi %(hi(0), g0)
-    const MachInst NoopMachInst = 0x01000000;
-
-    // These enumerate all the registers for dependence tracking.
-    enum DependenceTags {
-        FP_Base_DepTag = 32*3+9,
-        Ctrl_Base_DepTag = FP_Base_DepTag + 64
-    };
-
-    // semantically meaningful register indices
-    const int ZeroReg = 0;     // architecturally meaningful
-    // the rest of these depend on the ABI
-    const int StackPointerReg = 14;
-    const int ReturnAddressReg = 31; // post call, precall is 15
-    const int ReturnValueReg = 8; // Post return, 24 is pre-return.
-    const int FramePointerReg = 30;
-    const int ArgumentReg0 = 8;
-    const int ArgumentReg1 = 9;
-    const int ArgumentReg2 = 10;
-    const int ArgumentReg3 = 11;
-    const int ArgumentReg4 = 12;
-    const int ArgumentReg5 = 13;
-    // Some OS syscall use a second register (o1) to return a second value
-    const int SyscallPseudoReturnReg = ArgumentReg1;
-
-    //XXX These numbers are bogus
-    const int MaxInstSrcRegs = 8;
-    const int MaxInstDestRegs = 9;
-
-    //8K. This value is implmentation specific; and should probably
-    //be somewhere else.
-    const int LogVMPageSize = 13;
-    const int VMPageSize = (1 << LogVMPageSize);
-
-    // real address virtual mapping
-    // sort of like alpha super page, but less frequently used
-    const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
-    const Addr SegKPMBase = ULL(0xfffffac000000000);
-
-    //Why does both the previous set of constants and this one exist?
-    const int PageShift = 13;
-    const int PageBytes = 1ULL << PageShift;
-
-    const int BranchPredAddrShiftAmt = 2;
-
-    StaticInstPtr decodeInst(ExtMachInst);
-
-#if FULL_SYSTEM
-    // I don't know what it's for, so I don't
-    // know what SPARC's value should be
-    // For loading... XXX This maybe could be USegEnd?? --ali
-    const Addr LoadAddrMask = ULL(0xffffffffff);
-
-    /////////// TLB Stuff ////////////
-    const Addr StartVAddrHole = ULL(0x0000800000000000);
-    const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
-    const Addr VAddrAMask = ULL(0xFFFFFFFF);
-    const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
-    const Addr BytesInPageMask = ULL(0x1FFF);
-
-    enum InterruptTypes
-    {
-        IT_TRAP_LEVEL_ZERO,
-        IT_HINTP,
-        IT_INT_VEC,
-        IT_CPU_MONDO,
-        IT_DEV_MONDO,
-        IT_RES_ERROR,
-        IT_SOFT_INT,
-        NumInterruptTypes
-    };
-
-#endif
+const int MachineBytes = 8;
+
+// This makes sure the big endian versions of certain functions are used.
+using namespace BigEndianGuest;
+
+// SPARC has a delay slot
+#define ISA_HAS_DELAY_SLOT 1
+
+// SPARC NOP (sethi %(hi(0), g0)
+const MachInst NoopMachInst = 0x01000000;
+
+// 8K. This value is implmentation specific; and should probably
+// be somewhere else.
+const int LogVMPageSize = 13;
+const int VMPageSize = (1 << LogVMPageSize);
+
+// real address virtual mapping
+// sort of like alpha super page, but less frequently used
+const Addr SegKPMEnd  = ULL(0xfffffffc00000000);
+const Addr SegKPMBase = ULL(0xfffffac000000000);
+
+// Why does both the previous set of constants and this one exist?
+const int PageShift = 13;
+const int PageBytes = 1ULL << PageShift;
+
+const int BranchPredAddrShiftAmt = 2;
+
+StaticInstPtr decodeInst(ExtMachInst);
+
+/////////// TLB Stuff ////////////
+const Addr StartVAddrHole = ULL(0x0000800000000000);
+const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+const Addr VAddrAMask = ULL(0xFFFFFFFF);
+const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+const Addr BytesInPageMask = ULL(0x1FFF);
+
+enum InterruptTypes
+{
+    IT_TRAP_LEVEL_ZERO,
+    IT_HINTP,
+    IT_INT_VEC,
+    IT_CPU_MONDO,
+    IT_DEV_MONDO,
+    IT_RES_ERROR,
+    IT_SOFT_INT,
+    NumInterruptTypes
+};
+
+// Memory accesses cannot be unaligned
+const bool HasUnalignedMemAcc = false;
 }
 
 #endif // __ARCH_SPARC_ISA_TRAITS_HH__