"wstate",*/ "gl",
"hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
"hstick_cmpr",
- "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", "itbTsbC0Ps0",
- "itbTsbC0Ps1", "iTlbC0Cnfg", "itbTsbCXPs0", "itbTsbCXPs1",
- "iTlbCXCnfg","iTlbSfsr", "iTlbTagAcs", "dtbTsbC0Ps0",
- "dtbTsbC0Ps1", "dTlbC0Cnfg", "dtbTsbCXPs0", "dtbTsbCXPs1",
- "dTlbCXCnfg","dTlbSfsr", "dTlbSfar", "dTlbTagAcs",
+ "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
"scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
"scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
"devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
partId = 0;
lsuCtrlReg = 0;
- iTlbC0TsbPs0 = 0;
- iTlbC0TsbPs1 = 0;
- iTlbC0Config = 0;
- iTlbCXTsbPs0 = 0;
- iTlbCXTsbPs1 = 0;
- iTlbCXConfig = 0;
- iTlbSfsr = 0;
- iTlbTagAccess = 0;
-
- dTlbC0TsbPs0 = 0;
- dTlbC0TsbPs1 = 0;
- dTlbC0Config = 0;
- dTlbCXTsbPs0 = 0;
- dTlbCXTsbPs1 = 0;
- dTlbCXConfig = 0;
- dTlbSfsr = 0;
- dTlbSfar = 0;
- dTlbTagAccess = 0;
-
memset(scratchPad, 0, sizeof(scratchPad));
#if FULL_SYSTEM
tickCompare = NULL;
MiscReg MiscRegFile::readRegNoEffect(int miscReg)
{
- switch (miscReg) {
- case MISCREG_TLB_DATA:
- /* Package up all the data for the tlb:
- * 6666555555555544444444443333333333222222222211111111110000000000
- * 3210987654321098765432109876543210987654321098765432109876543210
- * secContext | priContext | |tl|partid| |||||^hpriv
- * ||||^red
- * |||^priv
- * ||^am
- * |^lsuim
- * ^lsudm
- */
- return bits((uint64_t)hpstate,2,2) |
- bits((uint64_t)hpstate,5,5) << 1 |
- bits((uint64_t)pstate,3,2) << 2 |
- bits((uint64_t)lsuCtrlReg,3,2) << 4 |
- bits((uint64_t)partId,7,0) << 8 |
- bits((uint64_t)tl,2,0) << 16 |
- (uint64_t)priContext << 32 |
- (uint64_t)secContext << 48;
+ // The three miscRegs are moved up from the switch statement
+ // due to more frequent calls.
+
+ if (miscReg == MISCREG_GL)
+ return gl;
+ if (miscReg == MISCREG_CWP)
+ return cwp;
+ if (miscReg == MISCREG_TLB_DATA) {
+ /* Package up all the data for the tlb:
+ * 6666555555555544444444443333333333222222222211111111110000000000
+ * 3210987654321098765432109876543210987654321098765432109876543210
+ * secContext | priContext | |tl|partid| |||||^hpriv
+ * ||||^red
+ * |||^priv
+ * ||^am
+ * |^lsuim
+ * ^lsudm
+ */
+ return bits((uint64_t)hpstate,2,2) |
+ bits((uint64_t)hpstate,5,5) << 1 |
+ bits((uint64_t)pstate,3,2) << 2 |
+ bits((uint64_t)lsuCtrlReg,3,2) << 4 |
+ bits((uint64_t)partId,7,0) << 8 |
+ bits((uint64_t)tl,2,0) << 16 |
+ (uint64_t)priContext << 32 |
+ (uint64_t)secContext << 48;
+ }
+
+ switch (miscReg) {
+ //case MISCREG_TLB_DATA:
+ // [original contents see above]
//case MISCREG_Y:
// return y;
//case MISCREG_CCR:
return tl;
case MISCREG_PIL:
return pil;
- case MISCREG_CWP:
- return cwp;
+ //CWP, GL moved
+ //case MISCREG_CWP:
+ // return cwp;
//case MISCREG_CANSAVE:
// return cansave;
//case MISCREG_CANRESTORE:
// return otherwin;
//case MISCREG_WSTATE:
// return wstate;
- case MISCREG_GL:
- return gl;
+ //case MISCREG_GL:
+ // return gl;
/** Hyper privileged registers */
case MISCREG_HPSTATE:
/** Floating Point Status Register */
case MISCREG_FSR:
- DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
+ DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
return fsr;
case MISCREG_MMU_P_CONTEXT:
case MISCREG_MMU_LSU_CTRL:
return lsuCtrlReg;
- case MISCREG_MMU_ITLB_C0_TSB_PS0:
- return iTlbC0TsbPs0;
- case MISCREG_MMU_ITLB_C0_TSB_PS1:
- return iTlbC0TsbPs1;
- case MISCREG_MMU_ITLB_C0_CONFIG:
- return iTlbC0Config;
- case MISCREG_MMU_ITLB_CX_TSB_PS0:
- return iTlbCXTsbPs0;
- case MISCREG_MMU_ITLB_CX_TSB_PS1:
- return iTlbCXTsbPs1;
- case MISCREG_MMU_ITLB_CX_CONFIG:
- return iTlbCXConfig;
- case MISCREG_MMU_ITLB_SFSR:
- return iTlbSfsr;
- case MISCREG_MMU_ITLB_TAG_ACCESS:
- return iTlbTagAccess;
-
- case MISCREG_MMU_DTLB_C0_TSB_PS0:
- return dTlbC0TsbPs0;
- case MISCREG_MMU_DTLB_C0_TSB_PS1:
- return dTlbC0TsbPs1;
- case MISCREG_MMU_DTLB_C0_CONFIG:
- return dTlbC0Config;
- case MISCREG_MMU_DTLB_CX_TSB_PS0:
- return dTlbCXTsbPs0;
- case MISCREG_MMU_DTLB_CX_TSB_PS1:
- return dTlbCXTsbPs1;
- case MISCREG_MMU_DTLB_CX_CONFIG:
- return dTlbCXConfig;
- case MISCREG_MMU_DTLB_SFSR:
- return dTlbSfsr;
- case MISCREG_MMU_DTLB_SFAR:
- return dTlbSfar;
- case MISCREG_MMU_DTLB_TAG_ACCESS:
- return dTlbTagAccess;
-
case MISCREG_SCRATCHPAD_R0:
return scratchPad[0];
case MISCREG_SCRATCHPAD_R1:
return readFSReg(miscReg, tc);
#else
case MISCREG_HPSTATE:
- //HPSTATE is special because because sometimes in privilege checks for instructions
- //it will read HPSTATE to make sure the priv. level is ok
- //So, we'll just have to tell it it isn't, instead of panicing.
+ //HPSTATE is special because because sometimes in privilege
+ //checks for instructions it will read HPSTATE to make sure
+ //the priv. level is ok So, we'll just have to tell it it
+ //isn't, instead of panicing.
return 0;
- panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
+ panic("Accessing Fullsystem register %s in SE mode\n",
+ getMiscRegName(miscReg));
#endif
}
/** Floating Point Status Register */
case MISCREG_FSR:
fsr = val;
- DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
+ DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
break;
case MISCREG_MMU_P_CONTEXT:
lsuCtrlReg = val;
break;
- case MISCREG_MMU_ITLB_C0_TSB_PS0:
- iTlbC0TsbPs0 = val;
- break;
- case MISCREG_MMU_ITLB_C0_TSB_PS1:
- iTlbC0TsbPs1 = val;
- break;
- case MISCREG_MMU_ITLB_C0_CONFIG:
- iTlbC0Config = val;
- break;
- case MISCREG_MMU_ITLB_CX_TSB_PS0:
- iTlbCXTsbPs0 = val;
- break;
- case MISCREG_MMU_ITLB_CX_TSB_PS1:
- iTlbCXTsbPs1 = val;
- break;
- case MISCREG_MMU_ITLB_CX_CONFIG:
- iTlbCXConfig = val;
- break;
- case MISCREG_MMU_ITLB_SFSR:
- iTlbSfsr = val;
- break;
- case MISCREG_MMU_ITLB_TAG_ACCESS:
- iTlbTagAccess = val;
- break;
-
- case MISCREG_MMU_DTLB_C0_TSB_PS0:
- dTlbC0TsbPs0 = val;
- break;
- case MISCREG_MMU_DTLB_C0_TSB_PS1:
- dTlbC0TsbPs1 = val;
- break;
- case MISCREG_MMU_DTLB_C0_CONFIG:
- dTlbC0Config = val;
- break;
- case MISCREG_MMU_DTLB_CX_TSB_PS0:
- dTlbCXTsbPs0 = val;
- break;
- case MISCREG_MMU_DTLB_CX_TSB_PS1:
- dTlbCXTsbPs1 = val;
- break;
- case MISCREG_MMU_DTLB_CX_CONFIG:
- dTlbCXConfig = val;
- break;
- case MISCREG_MMU_DTLB_SFSR:
- dTlbSfsr = val;
- break;
- case MISCREG_MMU_DTLB_SFAR:
- dTlbSfar = val;
- break;
- case MISCREG_MMU_DTLB_TAG_ACCESS:
- dTlbTagAccess = val;
- break;
-
case MISCREG_SCRATCHPAD_R0:
scratchPad[0] = val;
break;
tl = val;
#if FULL_SYSTEM
if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
- tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
+ tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
else
- tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
+ tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
#endif
return;
case MISCREG_CWP:
new_val = val >= NWindows ? NWindows - 1 : val;
- if (val >= NWindows) {
+ if (val >= NWindows)
new_val = NWindows - 1;
- warn("Attempted to set the CWP to %d with NWindows = %d\n",
- val, NWindows);
- }
- tc->changeRegFileContext(CONTEXT_CWP, new_val);
break;
case MISCREG_GL:
- tc->changeRegFileContext(CONTEXT_GLOBALS, val);
break;
case MISCREG_PIL:
case MISCREG_SOFTINT:
//HPSTATE is special because normal trap processing saves HPSTATE when
//it goes into a trap, and restores it when it returns.
return;
- panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
+ panic("Accessing Fullsystem register %s to %#x in SE mode\n",
+ getMiscRegName(miscReg), val);
#endif
}
setRegNoEffect(miscReg, new_val);
}
-void MiscRegFile::serialize(std::ostream & os)
+void
+MiscRegFile::serialize(EventManager *em, std::ostream &os)
{
SERIALIZE_SCALAR(asi);
SERIALIZE_SCALAR(tick);
SERIALIZE_SCALAR(secContext);
SERIALIZE_SCALAR(partId);
SERIALIZE_SCALAR(lsuCtrlReg);
- SERIALIZE_SCALAR(iTlbC0TsbPs0);
- SERIALIZE_SCALAR(iTlbC0TsbPs1);
- SERIALIZE_SCALAR(iTlbC0Config);
- SERIALIZE_SCALAR(iTlbCXTsbPs0);
- SERIALIZE_SCALAR(iTlbCXTsbPs1);
- SERIALIZE_SCALAR(iTlbCXConfig);
- SERIALIZE_SCALAR(iTlbSfsr);
- SERIALIZE_SCALAR(iTlbTagAccess);
- SERIALIZE_SCALAR(dTlbC0TsbPs0);
- SERIALIZE_SCALAR(dTlbC0TsbPs1);
- SERIALIZE_SCALAR(dTlbC0Config);
- SERIALIZE_SCALAR(dTlbCXTsbPs0);
- SERIALIZE_SCALAR(dTlbCXTsbPs1);
- SERIALIZE_SCALAR(dTlbCXConfig);
- SERIALIZE_SCALAR(dTlbSfsr);
- SERIALIZE_SCALAR(dTlbSfar);
- SERIALIZE_SCALAR(dTlbTagAccess);
SERIALIZE_ARRAY(scratchPad,8);
SERIALIZE_SCALAR(cpu_mondo_head);
SERIALIZE_SCALAR(cpu_mondo_tail);
#endif
}
-void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
+void
+MiscRegFile::unserialize(EventManager *em, Checkpoint *cp,
+ const string §ion)
{
UNSERIALIZE_SCALAR(asi);
UNSERIALIZE_SCALAR(tick);
UNSERIALIZE_SCALAR(secContext);
UNSERIALIZE_SCALAR(partId);
UNSERIALIZE_SCALAR(lsuCtrlReg);
- UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
- UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
- UNSERIALIZE_SCALAR(iTlbC0Config);
- UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
- UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
- UNSERIALIZE_SCALAR(iTlbCXConfig);
- UNSERIALIZE_SCALAR(iTlbSfsr);
- UNSERIALIZE_SCALAR(iTlbTagAccess);
- UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
- UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
- UNSERIALIZE_SCALAR(dTlbC0Config);
- UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
- UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
- UNSERIALIZE_SCALAR(dTlbCXConfig);
- UNSERIALIZE_SCALAR(dTlbSfsr);
- UNSERIALIZE_SCALAR(dTlbSfar);
- UNSERIALIZE_SCALAR(dTlbTagAccess);
UNSERIALIZE_ARRAY(scratchPad,8);
UNSERIALIZE_SCALAR(cpu_mondo_head);
UNSERIALIZE_SCALAR(cpu_mondo_tail);
if (tick_cmp) {
tickCompare = new TickCompareEvent(this, tc);
- tickCompare->schedule(tick_cmp);
+ em->schedule(tickCompare, tick_cmp);
}
if (stick_cmp) {
sTickCompare = new STickCompareEvent(this, tc);
- sTickCompare->schedule(stick_cmp);
+ em->schedule(sTickCompare, stick_cmp);
}
if (hstick_cmp) {
hSTickCompare = new HSTickCompareEvent(this, tc);
- hSTickCompare->schedule(hstick_cmp);
+ em->schedule(hSTickCompare, hstick_cmp);
}
}
}
projects / gem5.git / blobdiff