ISA: Set up common trace flags for tracing registers.

[gem5.git] / src / arch / sparc / miscregfile.cc

diff --git a/src/arch/sparc/miscregfile.cc b/src/arch/sparc/miscregfile.cc
index b22ceb657743b4133fad1eabfd46aab24f650ebf..e06d4b15a5b6ae5bfa2fe0d6d1fb01990e23c55c 100644 (file)
--- a/src/arch/sparc/miscregfile.cc
+++ b/src/arch/sparc/miscregfile.cc
@@ -227,7 +227,7 @@ MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 
         /** Floating Point Status Register */
       case MISCREG_FSR:
-        DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
+        DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
         return fsr;
 
       case MISCREG_MMU_P_CONTEXT:
@@ -446,7 +446,7 @@ void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
         /** Floating Point Status Register */
       case MISCREG_FSR:
         fsr = val;
-        DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
+        DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
         break;
 
       case MISCREG_MMU_P_CONTEXT: