MISCREG_MMU_PART_ID,
MISCREG_MMU_LSU_CTRL,
- MISCREG_MMU_ITLB_C0_TSB_PS0,
- MISCREG_MMU_ITLB_C0_TSB_PS1,
- MISCREG_MMU_ITLB_C0_CONFIG,
- MISCREG_MMU_ITLB_CX_TSB_PS0,
- MISCREG_MMU_ITLB_CX_TSB_PS1,
- MISCREG_MMU_ITLB_CX_CONFIG,
- MISCREG_MMU_ITLB_SFSR,
- MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
-
- MISCREG_MMU_DTLB_C0_TSB_PS0,
- MISCREG_MMU_DTLB_C0_TSB_PS1,
- MISCREG_MMU_DTLB_C0_CONFIG,
- MISCREG_MMU_DTLB_CX_TSB_PS0,
- MISCREG_MMU_DTLB_CX_TSB_PS1,
- MISCREG_MMU_DTLB_CX_CONFIG,
- MISCREG_MMU_DTLB_SFSR,
- MISCREG_MMU_DTLB_SFAR,
- MISCREG_MMU_DTLB_TAG_ACCESS,
-
/** Scratchpad regiscers **/
MISCREG_SCRATCHPAD_R0, /* 60 */
MISCREG_SCRATCHPAD_R1,
const static int ie = 0x2;
};
+ struct STS {
+ const static int st_idle = 0x00;
+ const static int st_wait = 0x01;
+ const static int st_halt = 0x02;
+ const static int st_run = 0x05;
+ const static int st_spec_run = 0x07;
+ const static int st_spec_rdy = 0x13;
+ const static int st_ready = 0x19;
+ const static int active = 0x01;
+ const static int speculative = 0x04;
+ const static int shft_id = 8;
+ const static int shft_fsm0 = 31;
+ const static int shft_fsm1 = 26;
+ const static int shft_fsm2 = 21;
+ const static int shft_fsm3 = 16;
+ };
+
const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
const int NumMiscRegs = MISCREG_NUMMISCREGS;
private:
/* ASR Registers */
- //uint64_t y; // Y (used in obsolete multiplication)
- //uint8_t ccr; // Condition Code Register
- uint8_t asi; // Address Space Identifier
- uint64_t tick; // Hardware clock-tick counter
- uint8_t fprs; // Floating-Point Register State
- uint64_t gsr; // General Status Register
+ //uint64_t y; // Y (used in obsolete multiplication)
+ //uint8_t ccr; // Condition Code Register
+ uint8_t asi; // Address Space Identifier
+ uint64_t tick; // Hardware clock-tick counter
+ uint8_t fprs; // Floating-Point Register State
+ uint64_t gsr; // General Status Register
uint64_t softint;
- uint64_t tick_cmpr; // Hardware tick compare registers
- uint64_t stick; // Hardware clock-tick counter
- uint64_t stick_cmpr; // Hardware tick compare registers
+ uint64_t tick_cmpr; // Hardware tick compare registers
+ uint64_t stick; // Hardware clock-tick counter
+ uint64_t stick_cmpr; // Hardware tick compare registers
/* Privileged Registers */
- uint64_t tpc[MaxTL]; // Trap Program Counter (value from
+ uint64_t tpc[MaxTL]; // Trap Program Counter (value from
// previous trap level)
- uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
+ uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
// previous trap level)
- uint64_t tstate[MaxTL]; // Trap State
- uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
+ uint64_t tstate[MaxTL]; // Trap State
+ uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
// on the previous level)
- uint64_t tba; // Trap Base Address
-
- uint16_t pstate; // Process State Register
- uint8_t tl; // Trap Level
- uint8_t pil; // Process Interrupt Register
- uint8_t cwp; // Current Window Pointer
- //uint8_t cansave; // Savable windows
- //uint8_t canrestore; // Restorable windows
- //uint8_t cleanwin; // Clean windows
- //uint8_t otherwin; // Other windows
- //uint8_t wstate; // Window State
+ uint64_t tba; // Trap Base Address
+
+ uint16_t pstate; // Process State Register
+ uint8_t tl; // Trap Level
+ uint8_t pil; // Process Interrupt Register
+ uint8_t cwp; // Current Window Pointer
+ //uint8_t cansave; // Savable windows
+ //uint8_t canrestore; // Restorable windows
+ //uint8_t cleanwin; // Clean windows
+ //uint8_t otherwin; // Other windows
+ //uint8_t wstate; // Window State
uint8_t gl; // Global level register
/** Hyperprivileged Registers */
- uint64_t hpstate; // Hyperprivileged State Register
+ uint64_t hpstate; // Hyperprivileged State Register
uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
uint64_t hintp;
- uint64_t htba; // Hyperprivileged Trap Base Address register
- uint64_t hstick_cmpr; // Hardware tick compare registers
+ uint64_t htba; // Hyperprivileged Trap Base Address register
+ uint64_t hstick_cmpr; // Hardware tick compare registers
uint64_t strandStatusReg;// Per strand status register
/** Floating point misc registers. */
- uint64_t fsr; // Floating-Point State Register
+ uint64_t fsr; // Floating-Point State Register
/** MMU Internal Registers */
uint16_t priContext;
uint16_t partId;
uint64_t lsuCtrlReg;
- uint64_t iTlbC0TsbPs0;
- uint64_t iTlbC0TsbPs1;
- uint64_t iTlbC0Config;
- uint64_t iTlbCXTsbPs0;
- uint64_t iTlbCXTsbPs1;
- uint64_t iTlbCXConfig;
- uint64_t iTlbSfsr;
- uint64_t iTlbTagAccess;
-
- uint64_t dTlbC0TsbPs0;
- uint64_t dTlbC0TsbPs1;
- uint64_t dTlbC0Config;
- uint64_t dTlbCXTsbPs0;
- uint64_t dTlbCXTsbPs1;
- uint64_t dTlbCXConfig;
- uint64_t dTlbSfsr;
- uint64_t dTlbSfar;
- uint64_t dTlbTagAccess;
-
uint64_t scratchPad[8];
uint64_t cpu_mondo_head;
// These need to check the int_dis field and if 0 then
// set appropriate bit in softint and checkinterrutps on the cpu
#if FULL_SYSTEM
- void setFSRegWithEffect(int miscReg, const MiscReg &val,
- ThreadContext *tc);
- MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
+ void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
+ MiscReg readFSReg(int miscReg, ThreadContext * tc);
// Update interrupt state on softint or pil change
void checkSoftInt(ThreadContext *tc);
clear();
}
- MiscReg readReg(int miscReg);
+ MiscReg readRegNoEffect(int miscReg);
- MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
+ MiscReg readReg(int miscReg, ThreadContext *tc);
- void setReg(int miscReg, const MiscReg &val);
+ void setRegNoEffect(int miscReg, const MiscReg &val);
- void setRegWithEffect(int miscReg,
+ void setReg(int miscReg,
const MiscReg &val, ThreadContext * tc);
int getInstAsid()
return priContext | (uint32_t)partId << 13;
}
- void serialize(std::ostream & os);
+ void serialize(EventManager *em, std::ostream & os);
- void unserialize(Checkpoint * cp, const std::string & section);
+ void unserialize(EventManager *em, Checkpoint *cp,
+ const std::string & section);
void copyMiscRegs(ThreadContext * tc);
projects / gem5.git / blobdiff