Merge zizzer:/bk/newmem

[gem5.git] / src / arch / sparc / miscregfile.hh

diff --git a/src/arch/sparc/miscregfile.hh b/src/arch/sparc/miscregfile.hh
index d09005795b7c9ec6b954566edd3093bcbe9a1241..ac0e930c5e88c1d93e46d1288aae435be396e9d4 100644 (file)
--- a/src/arch/sparc/miscregfile.hh
+++ b/src/arch/sparc/miscregfile.hh
@@ -39,6 +39,8 @@
 
 #include <string>
 
+class Checkpoint;
+
 namespace SparcISA
 {
     //These functions map register indices to names
@@ -47,8 +49,8 @@ namespace SparcISA
     enum MiscRegIndex
     {
         /** Ancillary State Registers */
-        MISCREG_Y, /* 0 */
-        MISCREG_CCR,
+//        MISCREG_Y,
+//        MISCREG_CCR,
         MISCREG_ASI,
         MISCREG_TICK,
         MISCREG_FPRS,
@@ -73,11 +75,11 @@ namespace SparcISA
         MISCREG_TL,
         MISCREG_PIL,
         MISCREG_CWP,
-        MISCREG_CANSAVE,
-        MISCREG_CANRESTORE,
-        MISCREG_CLEANWIN,
-        MISCREG_OTHERWIN,
-        MISCREG_WSTATE,
+//        MISCREG_CANSAVE,
+//        MISCREG_CANRESTORE,
+//        MISCREG_CLEANWIN,
+//        MISCREG_OTHERWIN,
+//        MISCREG_WSTATE,
         MISCREG_GL,
 
         /** Hyper privileged registers */
@@ -137,27 +139,31 @@ namespace SparcISA
         MISCREG_QUEUE_NRES_ERROR_HEAD,
         MISCREG_QUEUE_NRES_ERROR_TAIL,
 
+        /* All the data for the TLB packed up in one register. */
+        MISCREG_TLB_DATA,
         MISCREG_NUMMISCREGS
     };
 
-    enum HPStateFields {
-        id = 0x800,   // this impl. dependent (id) field must always be '1' for T1000
-        ibe = 0x400,
-        red = 0x20,
-        hpriv = 0x4,
-        tlz = 0x1
+    struct HPSTATE {
+        const static uint64_t id = 0x800;   // this impl. dependent (id) field m
+        const static uint64_t ibe = 0x400;
+        const static uint64_t red = 0x20;
+        const static uint64_t hpriv = 0x4;
+        const static uint64_t tlz = 0x1;
     };
 
-    enum PStateFields {
-        cle = 0x200,
-        tle = 0x100,
-        mm = 0xC0,
-        pef = 0x10,
-        am = 0x8,
-        priv = 0x4,
-        ie = 0x2
+
+    struct PSTATE {
+        const static int cle = 0x200;
+        const static int tle = 0x100;
+        const static int mm = 0xC0;
+        const static int pef = 0x10;
+        const static int am = 0x8;
+        const static int priv = 0x4;
+        const static int ie = 0x2;
     };
 
+
     const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
     const int NumMiscRegs = MISCREG_NUMMISCREGS;
 
@@ -167,8 +173,8 @@ namespace SparcISA
       private:
 
         /* ASR Registers */
-        uint64_t y;            // Y (used in obsolete multiplication)
-        uint8_t        ccr;            // Condition Code Register
+        //uint64_t y;          // Y (used in obsolete multiplication)
+        //uint8_t ccr;         // Condition Code Register
         uint8_t asi;           // Address Space Identifier
         uint64_t tick;         // Hardware clock-tick counter
         uint8_t        fprs;           // Floating-Point Register State
@@ -193,11 +199,11 @@ namespace SparcISA
         uint8_t tl;            // Trap Level
         uint8_t pil;           // Process Interrupt Register
         uint8_t cwp;           // Current Window Pointer
-        uint8_t cansave;       // Savable windows
-        uint8_t canrestore;    // Restorable windows
-        uint8_t cleanwin;      // Clean windows
-        uint8_t otherwin;      // Other windows
-        uint8_t wstate;                // Window State
+        //uint8_t cansave;     // Savable windows
+        //uint8_t canrestore;  // Restorable windows
+        //uint8_t cleanwin;    // Clean windows
+        //uint8_t otherwin;    // Other windows
+        //uint8_t wstate;              // Window State
         uint8_t gl;             // Global level register
 
         /** Hyperprivileged Registers */
@@ -255,6 +261,9 @@ namespace SparcISA
                 ThreadContext *tc);
         MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
 
+        // Update interrupt state on softint or pil change
+        void checkSoftInt(ThreadContext *tc);
+
         /** Process a tick compare event and generate an interrupt on the cpu if
          * appropriate. */
         void processTickCompare(ThreadContext *tc);