arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / nativetrace.cc

diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index 02d4f4dbf1382a7462dd65df989c478d303dd301..509e3adb9657554f70de59340feac32ddd5f8d32 100644 (file)
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -28,22 +28,24 @@
  * Authors: Gabe Black
  */
 
+#include "arch/sparc/nativetrace.hh"
+
 #include "arch/sparc/isa_traits.hh"
 #include "arch/sparc/registers.hh"
-#include "arch/sparc/nativetrace.hh"
 #include "cpu/thread_context.hh"
 #include "params/SparcNativeTrace.hh"
+#include "sim/byteswap.hh"
 
 namespace Trace {
 
 static const char *intRegNames[SparcISA::NumIntArchRegs] = {
-    //Global registers
+    // Global registers
     "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
-    //Output registers
+    // Output registers
     "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
-    //Local registers
+    // Local registers
     "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
-    //Input registers
+    // Input registers
     "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
 };
 
@@ -66,16 +68,17 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record)
         checkReg(*(regName++), regVal, realRegVal);
     }
 
+    SparcISA::PCState pc = tc->pcState();
     // PC
     read(&realRegVal, sizeof(realRegVal));
     realRegVal = SparcISA::gtoh(realRegVal);
-    regVal = tc->readNextPC();
+    regVal = pc.npc();
     checkReg("pc", regVal, realRegVal);
 
     // NPC
     read(&realRegVal, sizeof(realRegVal));
     realRegVal = SparcISA::gtoh(realRegVal);
-    regVal = tc->readNextNPC();
+    pc.nnpc();
     checkReg("npc", regVal, realRegVal);
 
     // CCR
@@ -85,7 +88,7 @@ Trace::SparcNativeTrace::check(NativeTraceRecord *record)
     checkReg("ccr", regVal, realRegVal);
 }
 
-} /* namespace Trace */
+} // namespace Trace
 
 ////////////////////////////////////////////////////////////////////////
 //