* Authors: Gabe Black
*/
+#include "arch/sparc/nativetrace.hh"
+
#include "arch/sparc/isa_traits.hh"
#include "arch/sparc/registers.hh"
-#include "arch/sparc/nativetrace.hh"
#include "cpu/thread_context.hh"
#include "params/SparcNativeTrace.hh"
+#include "sim/byteswap.hh"
namespace Trace {
-static char *intRegNames[SparcISA::NumIntArchRegs] = {
- //Global registers
+static const char *intRegNames[SparcISA::NumIntArchRegs] = {
+ // Global registers
"g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
- //Output registers
+ // Output registers
"o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
- //Local registers
+ // Local registers
"l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
- //Input registers
+ // Input registers
"i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
};
// I doubt a real SPARC will describe more integer registers than this.
assert(SparcISA::NumIntArchRegs == 32);
- char **regName = intRegNames;
+ const char **regName = intRegNames;
for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
regVal = tc->readIntReg(i);
read(&realRegVal, sizeof(realRegVal));
checkReg(*(regName++), regVal, realRegVal);
}
+ SparcISA::PCState pc = tc->pcState();
// PC
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
- regVal = tc->readNextPC();
+ regVal = pc.npc();
checkReg("pc", regVal, realRegVal);
// NPC
read(&realRegVal, sizeof(realRegVal));
realRegVal = SparcISA::gtoh(realRegVal);
- regVal = tc->readNextNPC();
+ pc.nnpc();
checkReg("npc", regVal, realRegVal);
// CCR
checkReg("ccr", regVal, realRegVal);
}
-} /* namespace Trace */
+} // namespace Trace
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//