syscall: Resolve conflicts between m5threads and Gabe's recent SE changes.

[gem5.git] / src / arch / sparc / predecoder.hh

diff --git a/src/arch/sparc/predecoder.hh b/src/arch/sparc/predecoder.hh
index 71b14b0201e4372613eb09a7cc976fa9636d711d..13ce5c1b6b5bc46842e30c210c0410e8c6f6b8b5 100644 (file)
--- a/src/arch/sparc/predecoder.hh
+++ b/src/arch/sparc/predecoder.hh
@@ -33,6 +33,7 @@
 
 #include "arch/sparc/types.hh"
 #include "base/misc.hh"
+#include "cpu/thread_context.hh"
 #include "sim/host.hh"
 
 class ThreadContext;
@@ -64,12 +65,13 @@ namespace SparcISA
         {
         }
 
+        void reset()
+        {}
+
         //Use this to give data to the predecoder. This should be used
         //when there is control flow.
-        void moreBytes(Addr currPC, Addr off, MachInst inst)
+        void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
         {
-            assert(off == 0);
-
             emi = inst;
             //The I bit, bit 13, is used to figure out where the ASI
             //should come from. Use that in the ExtMachInst. This is
@@ -84,13 +86,6 @@ namespace SparcISA
                         << (sizeof(MachInst) * 8));
         }
 
-        //Use this to give data to the predecoder. This should be used
-        //when instructions are executed in order.
-        void moreBytes(MachInst machInst)
-        {
-            moreBytes(0, 0, machInst);
-        }
-
         bool needMoreBytes()
         {
             return true;