arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / process.hh

diff --git a/src/arch/sparc/process.hh b/src/arch/sparc/process.hh
index 6a203a400d471264b04bbc757b330889d03277a1..eeb267116382f79fa42bac07c39d20e2bcfd1a70 100644 (file)
--- a/src/arch/sparc/process.hh
+++ b/src/arch/sparc/process.hh
@@ -109,11 +109,11 @@ class Sparc32Process : public SparcProcess
 
     void flushWindows(ThreadContext *tc);
 
-    SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RegVal getSyscallArg(ThreadContext *tc, int &i);
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
 
-    void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
+    void setSyscallArg(ThreadContext *tc, int i, RegVal val);
 };
 
 class Sparc64Process : public SparcProcess
@@ -153,14 +153,11 @@ class Sparc64Process : public SparcProcess
 
     void flushWindows(ThreadContext *tc);
 
-    SparcISA::IntReg getSyscallArg(ThreadContext *tc, int &i);
+    RegVal getSyscallArg(ThreadContext *tc, int &i);
     /// Explicitly import the otherwise hidden getSyscallArg
     using Process::getSyscallArg;
 
-    void setSyscallArg(ThreadContext *tc, int i, SparcISA::IntReg val);
+    void setSyscallArg(ThreadContext *tc, int i, RegVal val);
 };
 
-/* No architectural page table defined for this ISA */
-typedef NoArchPageTable ArchPageTable;
-
 #endif // __SPARC_PROCESS_HH__