#ifndef __ARCH_SPARC_REGISTERS_HH__
#define __ARCH_SPARC_REGISTERS_HH__
-#include "arch/sparc/max_inst_regs.hh"
+#include "arch/generic/vec_pred_reg.hh"
+#include "arch/generic/vec_reg.hh"
+#include "arch/sparc/generated/max_inst_regs.hh"
#include "arch/sparc/miscregs.hh"
#include "arch/sparc/sparc_traits.hh"
#include "base/types.hh"
namespace SparcISA
{
- using SparcISAInst::MaxInstSrcRegs;
- using SparcISAInst::MaxInstDestRegs;
- typedef uint64_t IntReg;
- typedef uint64_t MiscReg;
- typedef float FloatReg;
- typedef uint32_t FloatRegBits;
- typedef union
- {
- IntReg intReg;
- FloatReg fpreg;
- MiscReg ctrlreg;
- } AnyReg;
+using SparcISAInst::MaxInstSrcRegs;
+using SparcISAInst::MaxInstDestRegs;
+using SparcISAInst::MaxMiscDestRegs;
- typedef uint16_t RegIndex;
+// Not applicable to SPARC
+using VecElem = ::DummyVecElem;
+using VecReg = ::DummyVecReg;
+using ConstVecReg = ::DummyConstVecReg;
+using VecRegContainer = ::DummyVecRegContainer;
+constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg;
+constexpr size_t VecRegSizeBytes = ::DummyVecRegSizeBytes;
- // These enumerate all the registers for dependence tracking.
- enum DependenceTags {
- FP_Base_DepTag = 32*3+9,
- Ctrl_Base_DepTag = FP_Base_DepTag + 64,
- Max_DepTag = Ctrl_Base_DepTag + NumMiscRegs
- };
+// Not applicable to SPARC
+using VecPredReg = ::DummyVecPredReg;
+using ConstVecPredReg = ::DummyConstVecPredReg;
+using VecPredRegContainer = ::DummyVecPredRegContainer;
+constexpr size_t VecPredRegSizeBits = ::DummyVecPredRegSizeBits;
+constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
- // semantically meaningful register indices
- const int ZeroReg = 0; // architecturally meaningful
- // the rest of these depend on the ABI
- const int ReturnAddressReg = 31; // post call, precall is 15
- const int ReturnValueReg = 8; // Post return, 24 is pre-return.
- const int StackPointerReg = 14;
- const int FramePointerReg = 30;
+// semantically meaningful register indices
+const int ZeroReg = 0; // architecturally meaningful
+// the rest of these depend on the ABI
+const int ReturnAddressReg = 31; // post call, precall is 15
+const int ReturnValueReg = 8; // Post return, 24 is pre-return.
+const int StackPointerReg = 14;
+const int FramePointerReg = 30;
- // Some OS syscall use a second register (o1) to return a second value
- const int SyscallPseudoReturnReg = 9;
+// Some OS syscall use a second register (o1) to return a second value
+const int SyscallPseudoReturnReg = 9;
- const int NumIntArchRegs = 32;
- const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+const int NumIntArchRegs = 32;
+const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
+const int NumVecRegs = 1; // Not applicable to SPARC
+ // (1 to prevent warnings)
+const int NumVecPredRegs = 1; // Not applicable to SPARC
+ // (1 to prevent warnings)
+const int NumCCRegs = 0;
+
+const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
} // namespace SparcISA