arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / sparc_traits.hh

diff --git a/src/arch/sparc/sparc_traits.hh b/src/arch/sparc/sparc_traits.hh
index a3d29ea8a1d60f5a5a3ac61d0579048e60a00506..5f372926c53b93f04f04273044829e632865103a 100644 (file)
--- a/src/arch/sparc/sparc_traits.hh
+++ b/src/arch/sparc/sparc_traits.hh
@@ -33,23 +33,23 @@
 
 namespace SparcISA
 {
-    // Max trap levels
-    const int MaxPTL = 2;
-    const int MaxTL  = 6;
-    const int MaxGL  = 3;
-    const int MaxPGL = 2;
+// Max trap levels
+const int MaxPTL = 2;
+const int MaxTL  = 6;
+const int MaxGL  = 3;
+const int MaxPGL = 2;
 
-    // Number of register windows, can legally be 3 to 32
-    const int NWindows = 8;
-    const int NumMicroIntRegs = 1;
+// Number of register windows, can legally be 3 to 32
+const int NWindows = 8;
+// const int NumMicroIntRegs = 1;
+const int NumMicroIntRegs = 9;
 
-//    const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
-//    const int NumMicroIntRegs = 1;
-//    const int NumIntRegs =
-//     NumRegularIntRegs +
-//     NumMicroIntRegs;
-//    const int NumFloatRegs = 64;
-//    const int NumMiscRegs = 40;
+// const int NumRegularIntRegs = MaxGL * 8 + NWindows * 16;
+// const int NumMicroIntRegs = 1;
+// const int NumIntRegs = NumRegularIntRegs + NumMicroIntRegs;
+const int NumFloatRegs = 64;
+const int NumFloatArchRegs = NumFloatRegs;
+// const int NumMiscRegs = 40;
 }
 
-#endif // __ARCH_SPARC_ISA_TRAITS_HH__
+#endif // __ARCH_SPARC_SPARC_TRAITS_HH__