Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Inter...

[gem5.git] / src / arch / sparc / syscallreturn.hh

diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh
index c2494c3648e75ce4a7632905814fbc3f3b6746ca..cf13fc3e8f9a9cb5f4b2dc5f61055bbe3d5ffd7c 100644 (file)
--- a/src/arch/sparc/syscallreturn.hh
+++ b/src/arch/sparc/syscallreturn.hh
@@ -49,14 +49,14 @@ namespace SparcISA
             // no error, clear XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE);
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
             tc->setIntReg(ReturnValueReg, return_value.value());
         } else {
             // got an error, set XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) | 0x11);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11);
-            tc->setIntReg(ReturnValueReg, return_value.value());
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
+            tc->setIntReg(ReturnValueReg, -return_value.value());
         }
     }
 };