SCons: centralize the Dir() workaround for newer versions of scons.

[gem5.git] / src / arch / sparc / syscallreturn.hh

diff --git a/src/arch/sparc/syscallreturn.hh b/src/arch/sparc/syscallreturn.hh
index d92b1279048fd53366e4db6f4f74432b4d4d92fe..d4e6c7c509302c6a54be9ca5fd4a4639f02084c5 100644 (file)
--- a/src/arch/sparc/syscallreturn.hh
+++ b/src/arch/sparc/syscallreturn.hh
@@ -49,14 +49,24 @@ namespace SparcISA
             // no error, clear XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) & 0xEE);
-            tc->setIntReg(ReturnValueReg, return_value.value());
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
+            IntReg val = return_value.value();
+            if (bits(tc->readMiscRegNoEffect(
+                            SparcISA::MISCREG_PSTATE), 3, 3)) {
+                val = bits(val, 31, 0);
+            }
+            tc->setIntReg(ReturnValueReg, val);
         } else {
             // got an error, set XCC.C
             tc->setIntReg(NumIntArchRegs + 2,
                     tc->readIntReg(NumIntArchRegs + 2) | 0x11);
-            //tc->setMiscReg(MISCREG_CCR, tc->readMiscReg(MISCREG_CCR) | 0x11);
-            tc->setIntReg(ReturnValueReg, -return_value.value());
+            //tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
+            IntReg val = -return_value.value();
+            if (bits(tc->readMiscRegNoEffect(
+                            SparcISA::MISCREG_PSTATE), 3, 3)) {
+                val = bits(val, 31, 0);
+            }
+            tc->setIntReg(ReturnValueReg, val);
         }
     }
 };