arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / tlb.hh

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index d563772e6ac8ea69c7dd294764be24c53388b17d..0d173da3230d3944b65056ce1f51b5c9f1a54eb3 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,15 +31,12 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "arch/generic/tlb.hh"
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
-#include "base/misc.hh"
-#include "config/full_system.hh"
+#include "base/logging.hh"
 #include "mem/request.hh"
-#include "params/SparcDTB.hh"
-#include "params/SparcITB.hh"
-#include "sim/faults.hh"
-#include "sim/tlb.hh"
+#include "params/SparcTLB.hh"
 
 class ThreadContext;
 class Packet;
@@ -47,16 +44,21 @@ class Packet;
 namespace SparcISA
 {
 
+const Addr StartVAddrHole = ULL(0x0000800000000000);
+const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+const Addr VAddrAMask = ULL(0xFFFFFFFF);
+const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+
 class TLB : public BaseTLB
 {
-#if !FULL_SYSTEM
-    //These faults need to be able to populate the tlb in SE mode.
+    // These faults need to be able to populate the tlb in SE mode.
     friend class FastInstructionAccessMMUMiss;
     friend class FastDataAccessMMUMiss;
-#endif
 
-    //TLB state
+    // TLB state
   protected:
+    // Only used when this is the data TLB.
+    uint64_t sfar;
     uint64_t c0_tsb_ps0;
     uint64_t c0_tsb_ps1;
     uint64_t c0_config;
@@ -116,6 +118,10 @@ class TLB : public BaseTLB
      */
     TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
             bool update_used = true);
+
+    /** Remove all entries from the TLB */
+    void flushAll() override;
+
   protected:
     /** Insert a PTE into the TLB. */
     void insert(Addr vpn, int partition_id, int context_id, bool real,
@@ -124,9 +130,6 @@ class TLB : public BaseTLB
     /** Given an entry id, read that tlb entries' tag. */
     uint64_t TagRead(int entry);
 
-    /** Remove all entries from the TLB */
-    void invalidateAll();
-
     /** Remove all non-locked entries from the tlb that match partition id. */
     void demapAll(int partition_id);
 
@@ -148,68 +151,42 @@ class TLB : public BaseTLB
 
     void writeTagAccess(Addr va, int context);
 
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
+
   public:
     typedef SparcTLBParams Params;
     TLB(const Params *p);
 
-    void demapPage(Addr vaddr, uint64_t asn)
+    void takeOverFrom(BaseTLB *otlb) override {}
+
+    void
+    demapPage(Addr vaddr, uint64_t asn) override
     {
         panic("demapPage(Addr) is not implemented.\n");
     }
 
     void dumpAll();
 
+    Fault translateAtomic(
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
+    void translateTiming(
+            const RequestPtr &req, ThreadContext *tc,
+            Translation *translation, Mode mode) override;
+    Fault finalizePhysical(
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
+    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
+
     // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
 
     /** Give an entry id, read that tlb entries' tte */
     uint64_t TteRead(int entry);
 
-};
-
-class ITB : public TLB
-{
-  public:
-    typedef SparcITBParams Params;
-    ITB(const Params *p) : TLB(p)
-    {
-        cacheEntry = NULL;
-    }
-
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc);
-  private:
-    void writeSfsr(bool write, ContextType ct,
-            bool se, FaultTypes ft, int asi);
-    TlbEntry *cacheEntry;
-    friend class DTB;
-};
-
-class DTB : public TLB
-{
-    //DTLB specific state
-  protected:
-    uint64_t sfar;
-  public:
-    typedef SparcDTBParams Params;
-    DTB(const Params *p) : TLB(p)
-    {
-        sfar = 0;
-        cacheEntry[0] = NULL;
-        cacheEntry[1] = NULL;
-    }
-
-    Fault translateAtomic(RequestPtr &req, ThreadContext *tc, bool write);
-#if FULL_SYSTEM
-    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-#endif
-    void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
-
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
   private:
     void writeSfsr(Addr a, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);