arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / tlb.hh

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index e1111db8dbc50e8e76f89662606387bcd74aea1d..0d173da3230d3944b65056ce1f51b5c9f1a54eb3 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,12 +31,12 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "arch/generic/tlb.hh"
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/tlb_map.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "mem/request.hh"
-#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "params/SparcTLB.hh"
 
 class ThreadContext;
 class Packet;
@@ -44,10 +44,21 @@ class Packet;
 namespace SparcISA
 {
 
-class TLB : public SimObject
+const Addr StartVAddrHole = ULL(0x0000800000000000);
+const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+const Addr VAddrAMask = ULL(0xFFFFFFFF);
+const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+
+class TLB : public BaseTLB
 {
-    //TLB state
+    // These faults need to be able to populate the tlb in SE mode.
+    friend class FastInstructionAccessMMUMiss;
+    friend class FastDataAccessMMUMiss;
+
+    // TLB state
   protected:
+    // Only used when this is the data TLB.
+    uint64_t sfar;
     uint64_t c0_tsb_ps0;
     uint64_t c0_tsb_ps1;
     uint64_t c0_config;
@@ -100,13 +111,17 @@ class TLB : public SimObject
      * @param paritition_id partition this entry is for
      * @param real is this a real->phys or virt->phys translation
      * @param context_id if this is virt->phys what context
-     * @param update_used should ew update the used bits in the entries on not
-     * useful if we are trying to do a va->pa without mucking with any state for
-     * a debug read for example.
+     * @param update_used should ew update the used bits in the
+     * entries on not useful if we are trying to do a va->pa without
+     * mucking with any state for a debug read for example.
      * @return A pointer to a tlb entry
      */
     TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
             bool update_used = true);
+
+    /** Remove all entries from the TLB */
+    void flushAll() override;
+
   protected:
     /** Insert a PTE into the TLB. */
     void insert(Addr vpn, int partition_id, int context_id, bool real,
@@ -115,9 +130,6 @@ class TLB : public SimObject
     /** Given an entry id, read that tlb entries' tag. */
     uint64_t TagRead(int entry);
 
-    /** Remove all entries from the TLB */
-    void invalidateAll();
-
     /** Remove all non-locked entries from the tlb that match partition id. */
     void demapAll(int partition_id);
 
@@ -139,57 +151,41 @@ class TLB : public SimObject
 
     void writeTagAccess(Addr va, int context);
 
-  public:
-    TLB(const std::string &name, int size);
-
-    void dumpAll();
-
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    /** Give an entry id, read that tlb entries' tte */
-    uint64_t TteRead(int entry);
-
-};
+    Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+    Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
 
-class ITB : public TLB
-{
   public:
-    ITB(const std::string &name, int size) : TLB(name, size)
-    {
-        cacheEntry = NULL;
-    }
+    typedef SparcTLBParams Params;
+    TLB(const Params *p);
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-  private:
-    void writeSfsr(bool write, ContextType ct,
-            bool se, FaultTypes ft, int asi);
-    TlbEntry *cacheEntry;
-    friend class DTB;
-};
+    void takeOverFrom(BaseTLB *otlb) override {}
 
-class DTB : public TLB
-{
-    //DTLB specific state
-  protected:
-    uint64_t sfar;
-  public:
-    DTB(const std::string &name, int size) : TLB(name, size)
+    void
+    demapPage(Addr vaddr, uint64_t asn) override
     {
-        sfar = 0;
-        cacheEntry[0] = NULL;
-        cacheEntry[1] = NULL;
+        panic("demapPage(Addr) is not implemented.\n");
     }
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
-    Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
-    Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+    void dumpAll();
+
+    Fault translateAtomic(
+            const RequestPtr &req, ThreadContext *tc, Mode mode) override;
+    void translateTiming(
+            const RequestPtr &req, ThreadContext *tc,
+            Translation *translation, Mode mode) override;
+    Fault finalizePhysical(
+            const RequestPtr &req,
+            ThreadContext *tc, Mode mode) const override;
+    Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
+    Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
     void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
 
     // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
+    void serialize(CheckpointOut &cp) const override;
+    void unserialize(CheckpointIn &cp) override;
+
+    /** Give an entry id, read that tlb entries' tte */
+    uint64_t TteRead(int entry);
 
   private:
     void writeSfsr(Addr a, bool write, ContextType ct,