#include "arch/generic/tlb.hh"
#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
#include "mem/request.hh"
#include "params/SparcTLB.hh"
namespace SparcISA
{
+const Addr StartVAddrHole = ULL(0x0000800000000000);
+const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
+const Addr VAddrAMask = ULL(0xFFFFFFFF);
+const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
+
class TLB : public BaseTLB
{
// These faults need to be able to populate the tlb in SE mode.
bool update_used = true);
/** Remove all entries from the TLB */
- void flushAll();
+ void flushAll() override;
protected:
/** Insert a PTE into the TLB. */
void writeTagAccess(Addr va, int context);
- Fault translateInst(RequestPtr req, ThreadContext *tc);
- Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+ Fault translateInst(const RequestPtr &req, ThreadContext *tc);
+ Fault translateData(const RequestPtr &req, ThreadContext *tc, bool write);
public:
typedef SparcTLBParams Params;
TLB(const Params *p);
- void takeOverFrom(BaseTLB *otlb) {}
+ void takeOverFrom(BaseTLB *otlb) override {}
void
- demapPage(Addr vaddr, uint64_t asn)
+ demapPage(Addr vaddr, uint64_t asn) override
{
panic("demapPage(Addr) is not implemented.\n");
}
void dumpAll();
- Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
- void translateTiming(RequestPtr req, ThreadContext *tc,
- Translation *translation, Mode mode);
- /** Stub function for compilation support with CheckerCPU. SPARC ISA
- * does not support the Checker model at the moment
- */
- Fault translateFunctional(RequestPtr req, ThreadContext *tc, Mode mode);
- Fault finalizePhysical(RequestPtr req, ThreadContext *tc, Mode mode) const;
+ Fault translateAtomic(
+ const RequestPtr &req, ThreadContext *tc, Mode mode) override;
+ void translateTiming(
+ const RequestPtr &req, ThreadContext *tc,
+ Translation *translation, Mode mode) override;
+ Fault finalizePhysical(
+ const RequestPtr &req,
+ ThreadContext *tc, Mode mode) const override;
Cycles doMmuRegRead(ThreadContext *tc, Packet *pkt);
Cycles doMmuRegWrite(ThreadContext *tc, Packet *pkt);
void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
// Checkpointing
- void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE;
- void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE;
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
/** Give an entry id, read that tlb entries' tte */
uint64_t TteRead(int entry);