Stubs for SPARC's tlbs

[gem5.git] / src / arch / sparc / tlb.hh

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index 0d42e2c97acb842904b0c605016f26c2fe4cd0d7..0fdba6baf3d371f176c67b8b66d2d55b73b99dd2 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -31,19 +31,29 @@
 #ifndef __ARCH_SPARC_TLB_HH__
 #define __ARCH_SPARC_TLB_HH__
 
+#include "mem/request.hh"
 #include "sim/faults.hh"
+#include "sim/sim_object.hh"
 
 class ThreadContext;
 
 namespace SparcISA
 {
-    class TLB
+    class TLB : public SimObject
     {
+      public:
+        TLB(const std::string &name, int size) : SimObject(name)
+        {
+        }
     };
 
     class ITB : public TLB
     {
       public:
+        ITB(const std::string &name, int size) : TLB(name, size)
+        {
+        }
+
         Fault translate(RequestPtr &req, ThreadContext *tc) const
         {
             return NoFault;
@@ -53,6 +63,10 @@ namespace SparcISA
     class DTB : public TLB
     {
       public:
+        DTB(const std::string &name, int size) : TLB(name, size)
+        {
+        }
+
         Fault translate(RequestPtr &req, ThreadContext *tc, bool write) const
         {
             return NoFault;