#include "arch/sparc/asi.hh"
#include "arch/sparc/tlb_map.hh"
#include "base/misc.hh"
+#include "config/full_system.hh"
#include "mem/request.hh"
+#include "params/SparcTLB.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
class Packet;
namespace SparcISA
{
-class TLB : public SimObject
+class TLB : public BaseTLB
{
+#if !FULL_SYSTEM
+ //These faults need to be able to populate the tlb in SE mode.
+ friend class FastInstructionAccessMMUMiss;
+ friend class FastDataAccessMMUMiss;
+#endif
+
+ //TLB state
+ protected:
+ // Only used when this is the data TLB.
+ uint64_t sfar;
+ uint64_t c0_tsb_ps0;
+ uint64_t c0_tsb_ps1;
+ uint64_t c0_config;
+ uint64_t cx_tsb_ps0;
+ uint64_t cx_tsb_ps1;
+ uint64_t cx_config;
+ uint64_t sfsr;
+ uint64_t tag_access;
+
protected:
TlbMap lookupTable;;
typedef TlbMap::iterator MapIter;
int size;
int usedEntries;
+ int lastReplaced;
uint64_t cacheState;
bool cacheValid;
+ std::list<TlbEntry*> freeList;
+
enum FaultTypes {
OtherFault = 0,
PrivViolation = 0x1,
Nucleus = 2
};
-
+ enum TsbPageSize {
+ Ps0,
+ Ps1
+ };
+ public:
/** lookup an entry in the TLB based on the partition id, and real bit if
* real is true or the partition id, and context id if real is false.
* @param va the virtual address not shifted (e.g. bottom 13 bits are 0)
* @param paritition_id partition this entry is for
* @param real is this a real->phys or virt->phys translation
* @param context_id if this is virt->phys what context
+ * @param update_used should ew update the used bits in the
+ * entries on not useful if we are trying to do a va->pa without
+ * mucking with any state for a debug read for example.
* @return A pointer to a tlb entry
*/
- TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0);
-
+ TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
+ bool update_used = true);
+ protected:
/** Insert a PTE into the TLB. */
void insert(Addr vpn, int partition_id, int context_id, bool real,
const PageTableEntry& PTE, int entry = -1);
/** Given an entry id, read that tlb entries' tag. */
uint64_t TagRead(int entry);
- /** Give an entry id, read that tlb entries' tte */
- uint64_t TteRead(int entry);
-
/** Remove all entries from the TLB */
void invalidateAll();
/** Checks if the virtual address provided is a valid one. */
bool validVirtualAddress(Addr va, bool am);
- void writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct,
+ void writeSfsr(bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
void clearUsedBits();
- void writeTagAccess(ThreadContext *tc, int reg, Addr va, int context);
+ void writeTagAccess(Addr va, int context);
+
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
public:
- TLB(const std::string &name, int size);
+ typedef SparcTLBParams Params;
+ TLB(const Params *p);
+
+ void demapPage(Addr vaddr, uint64_t asn)
+ {
+ panic("demapPage(Addr) is not implemented.\n");
+ }
void dumpAll();
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
+#if FULL_SYSTEM
+ Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
+ Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
+#endif
+ void GetTsbPtr(ThreadContext *tc, Addr addr, int ctx, Addr *ptrs);
+
// Checkpointing
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
-};
-class ITB : public TLB
-{
- public:
- ITB(const std::string &name, int size) : TLB(name, size)
- {
- cacheEntry = NULL;
- }
+ /** Give an entry id, read that tlb entries' tte */
+ uint64_t TteRead(int entry);
- Fault translate(RequestPtr &req, ThreadContext *tc);
private:
- void writeSfsr(ThreadContext *tc, bool write, ContextType ct,
+ void writeSfsr(Addr a, bool write, ContextType ct,
bool se, FaultTypes ft, int asi);
- void writeTagAccess(ThreadContext *tc, Addr va, int context);
- TlbEntry *cacheEntry;
- friend class DTB;
-};
-class DTB : public TLB
-{
- public:
- DTB(const std::string &name, int size) : TLB(name, size)
- {
- cacheEntry[0] = NULL;
- cacheEntry[1] = NULL;
- }
+ uint64_t MakeTsbPtr(TsbPageSize ps, uint64_t tag_access, uint64_t c0_tsb,
+ uint64_t c0_config, uint64_t cX_tsb, uint64_t cX_config);
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
- Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
- Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
-
- private:
- void writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
- bool se, FaultTypes ft, int asi);
- void writeTagAccess(ThreadContext *tc, Addr va, int context);
TlbEntry *cacheEntry[2];
ASI cacheAsi[2];