#include "base/misc.hh"
#include "config/full_system.hh"
#include "mem/request.hh"
+#include "params/SparcTLB.hh"
#include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
class ThreadContext;
class Packet;
namespace SparcISA
{
-class TLB : public SimObject
+class TLB : public BaseTLB
{
#if !FULL_SYSTEM
//These faults need to be able to populate the tlb in SE mode.
//TLB state
protected:
+ // Only used when this is the data TLB.
+ uint64_t sfar;
uint64_t c0_tsb_ps0;
uint64_t c0_tsb_ps1;
uint64_t c0_config;
* @param paritition_id partition this entry is for
* @param real is this a real->phys or virt->phys translation
* @param context_id if this is virt->phys what context
- * @param update_used should ew update the used bits in the entries on not
- * useful if we are trying to do a va->pa without mucking with any state for
- * a debug read for example.
+ * @param update_used should ew update the used bits in the
+ * entries on not useful if we are trying to do a va->pa without
+ * mucking with any state for a debug read for example.
* @return A pointer to a tlb entry
*/
TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
void writeTagAccess(Addr va, int context);
- public:
- TLB(const std::string &name, int size);
-
- void dumpAll();
-
- // Checkpointing
- virtual void serialize(std::ostream &os);
- virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ Fault translateInst(RequestPtr req, ThreadContext *tc);
+ Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
- /** Give an entry id, read that tlb entries' tte */
- uint64_t TteRead(int entry);
-
-};
-
-class ITB : public TLB
-{
public:
- ITB(const std::string &name, int size) : TLB(name, size)
- {
- cacheEntry = NULL;
- }
-
- Fault translate(RequestPtr &req, ThreadContext *tc);
- private:
- void writeSfsr(bool write, ContextType ct,
- bool se, FaultTypes ft, int asi);
- TlbEntry *cacheEntry;
- friend class DTB;
-};
+ typedef SparcTLBParams Params;
+ TLB(const Params *p);
-class DTB : public TLB
-{
- //DTLB specific state
- protected:
- uint64_t sfar;
- public:
- DTB(const std::string &name, int size) : TLB(name, size)
+ void demapPage(Addr vaddr, uint64_t asn)
{
- sfar = 0;
- cacheEntry[0] = NULL;
- cacheEntry[1] = NULL;
+ panic("demapPage(Addr) is not implemented.\n");
}
- Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+ void dumpAll();
+
+ Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+ void translateTiming(RequestPtr req, ThreadContext *tc,
+ Translation *translation, Mode mode);
#if FULL_SYSTEM
Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
virtual void serialize(std::ostream &os);
virtual void unserialize(Checkpoint *cp, const std::string §ion);
+ /** Give an entry id, read that tlb entries' tte */
+ uint64_t TteRead(int entry);
+
private:
void writeSfsr(Addr a, bool write, ContextType ct,
bool se, FaultTypes ft, int asi);