SE mode: Make keeping track of the number of syscalls less hacky.

[gem5.git] / src / arch / sparc / tlb.hh

diff --git a/src/arch/sparc/tlb.hh b/src/arch/sparc/tlb.hh
index b38ee15dc87c27c01ad4dd3e7f8c74256d3d4b55..76b6870421943d394345213bf61694f104e3c221 100644 (file)
--- a/src/arch/sparc/tlb.hh
+++ b/src/arch/sparc/tlb.hh
@@ -36,10 +36,9 @@
 #include "base/misc.hh"
 #include "config/full_system.hh"
 #include "mem/request.hh"
-#include "params/SparcDTB.hh"
-#include "params/SparcITB.hh"
+#include "params/SparcTLB.hh"
 #include "sim/faults.hh"
-#include "sim/sim_object.hh"
+#include "sim/tlb.hh"
 
 class ThreadContext;
 class Packet;
@@ -47,7 +46,7 @@ class Packet;
 namespace SparcISA
 {
 
-class TLB : public SimObject
+class TLB : public BaseTLB
 {
 #if !FULL_SYSTEM
     //These faults need to be able to populate the tlb in SE mode.
@@ -57,6 +56,8 @@ class TLB : public SimObject
 
     //TLB state
   protected:
+    // Only used when this is the data TLB.
+    uint64_t sfar;
     uint64_t c0_tsb_ps0;
     uint64_t c0_tsb_ps1;
     uint64_t c0_config;
@@ -109,9 +110,9 @@ class TLB : public SimObject
      * @param paritition_id partition this entry is for
      * @param real is this a real->phys or virt->phys translation
      * @param context_id if this is virt->phys what context
-     * @param update_used should ew update the used bits in the entries on not
-     * useful if we are trying to do a va->pa without mucking with any state for
-     * a debug read for example.
+     * @param update_used should ew update the used bits in the
+     * entries on not useful if we are trying to do a va->pa without
+     * mucking with any state for a debug read for example.
      * @return A pointer to a tlb entry
      */
     TlbEntry *lookup(Addr va, int partition_id, bool real, int context_id = 0,
@@ -148,53 +149,23 @@ class TLB : public SimObject
 
     void writeTagAccess(Addr va, int context);
 
+    Fault translateInst(RequestPtr req, ThreadContext *tc);
+    Fault translateData(RequestPtr req, ThreadContext *tc, bool write);
+
   public:
     typedef SparcTLBParams Params;
     TLB(const Params *p);
 
-    void dumpAll();
-
-    // Checkpointing
-    virtual void serialize(std::ostream &os);
-    virtual void unserialize(Checkpoint *cp, const std::string &section);
-
-    /** Give an entry id, read that tlb entries' tte */
-    uint64_t TteRead(int entry);
-
-};
-
-class ITB : public TLB
-{
-  public:
-    typedef SparcITBParams Params;
-    ITB(const Params *p) : TLB(p)
+    void demapPage(Addr vaddr, uint64_t asn)
     {
-        cacheEntry = NULL;
+        panic("demapPage(Addr) is not implemented.\n");
     }
 
-    Fault translate(RequestPtr &req, ThreadContext *tc);
-  private:
-    void writeSfsr(bool write, ContextType ct,
-            bool se, FaultTypes ft, int asi);
-    TlbEntry *cacheEntry;
-    friend class DTB;
-};
-
-class DTB : public TLB
-{
-    //DTLB specific state
-  protected:
-    uint64_t sfar;
-  public:
-    typedef SparcDTBParams Params;
-    DTB(const Params *p) : TLB(p)
-    {
-        sfar = 0;
-        cacheEntry[0] = NULL;
-        cacheEntry[1] = NULL;
-    }
+    void dumpAll();
 
-    Fault translate(RequestPtr &req, ThreadContext *tc, bool write);
+    Fault translateAtomic(RequestPtr req, ThreadContext *tc, Mode mode);
+    void translateTiming(RequestPtr req, ThreadContext *tc,
+            Translation *translation, Mode mode);
 #if FULL_SYSTEM
     Tick doMmuRegRead(ThreadContext *tc, Packet *pkt);
     Tick doMmuRegWrite(ThreadContext *tc, Packet *pkt);
@@ -205,6 +176,9 @@ class DTB : public TLB
     virtual void serialize(std::ostream &os);
     virtual void unserialize(Checkpoint *cp, const std::string &section);
 
+    /** Give an entry id, read that tlb entries' tte */
+    uint64_t TteRead(int entry);
+
   private:
     void writeSfsr(Addr a, bool write, ContextType ct,
             bool se, FaultTypes ft, int asi);