arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / types.hh

diff --git a/src/arch/sparc/types.hh b/src/arch/sparc/types.hh
index 15386adcafbec240a08190a362f65d73e91d6281..a0f757df3c87338164bf8bca4d66cc5faa844279 100644 (file)
--- a/src/arch/sparc/types.hh
+++ b/src/arch/sparc/types.hh
@@ -31,35 +31,17 @@
 #ifndef __ARCH_SPARC_TYPES_HH__
 #define __ARCH_SPARC_TYPES_HH__
 
-#include <inttypes.h>
-#include "base/bigint.hh"
+#include "arch/generic/types.hh"
+#include "base/types.hh"
 
 namespace SparcISA
 {
-    typedef uint32_t MachInst;
-    typedef uint64_t ExtMachInst;
 
-    typedef uint64_t IntReg;
-    typedef Twin64_t LargestRead;
-    typedef uint64_t MiscReg;
-    typedef double FloatReg;
-    typedef uint64_t FloatRegBits;
-    typedef union
-    {
-        IntReg intReg;
-        FloatReg fpreg;
-        MiscReg ctrlreg;
-    } AnyReg;
+typedef uint32_t MachInst;
+typedef uint64_t ExtMachInst;
 
-    enum RegContextParam
-    {
-        CONTEXT_CWP,
-        CONTEXT_GLOBALS
-    };
+typedef GenericISA::DelaySlotUPCState<MachInst> PCState;
 
-    typedef int RegContextVal;
-
-    typedef uint8_t RegIndex;
 }
 
 #endif