arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / ua2005.cc

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index 274301b3704f829d332b4d54b1306a8d231bbc2a..389549b40c42ab1ed764a337a8fd83c291b7c35b 100644 (file)
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa.hh"
 #include "arch/sparc/kernel_stats.hh"
 #include "arch/sparc/registers.hh"
@@ -88,7 +89,7 @@ getMiscRegName(RegIndex index)
 }
 
 void
-ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
 {
     BaseCPU *cpu = tc->getCpuPtr();
 
@@ -137,6 +138,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
 
       case MISCREG_PSTATE:
         setMiscRegNoEffect(miscReg, val);
+        break;
 
       case MISCREG_PIL:
         setMiscRegNoEffect(miscReg, val);
@@ -241,7 +243,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
     }
 }
 
-MiscReg
+RegVal
 ISA::readFSReg(int miscReg, ThreadContext * tc)
 {
     uint64_t temp;