arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / ua2005.cc

diff --git a/src/arch/sparc/ua2005.cc b/src/arch/sparc/ua2005.cc
index b207f2fac9957b0a77c04ef7fb5e443997976e6e..389549b40c42ab1ed764a337a8fd83c291b7c35b 100644 (file)
--- a/src/arch/sparc/ua2005.cc
+++ b/src/arch/sparc/ua2005.cc
@@ -26,6 +26,7 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "arch/sparc/interrupts.hh"
 #include "arch/sparc/isa.hh"
 #include "arch/sparc/kernel_stats.hh"
 #include "arch/sparc/registers.hh"
@@ -35,8 +36,8 @@
 #include "cpu/thread_context.hh"
 #include "debug/Quiesce.hh"
 #include "debug/Timer.hh"
-#include "sim/system.hh"
 #include "sim/full_system.hh"
+#include "sim/system.hh"
 
 using namespace SparcISA;
 using namespace std;
@@ -49,20 +50,20 @@ ISA::checkSoftInt(ThreadContext *tc)
 
     // If PIL < 14, copy over the tm and sm bits
     if (pil < 14 && softint & 0x10000)
-        cpu->postInterrupt(IT_SOFT_INT, 16);
+        cpu->postInterrupt(0, IT_SOFT_INT, 16);
     else
-        cpu->clearInterrupt(IT_SOFT_INT, 16);
+        cpu->clearInterrupt(0, IT_SOFT_INT, 16);
     if (pil < 14 && softint & 0x1)
-        cpu->postInterrupt(IT_SOFT_INT, 0);
+        cpu->postInterrupt(0, IT_SOFT_INT, 0);
     else
-        cpu->clearInterrupt(IT_SOFT_INT, 0);
+        cpu->clearInterrupt(0, IT_SOFT_INT, 0);
 
     // Copy over any of the other bits that are set
     for (int bit = 15; bit > 0; --bit) {
         if (1 << bit & softint && bit > pil)
-            cpu->postInterrupt(IT_SOFT_INT, bit);
+            cpu->postInterrupt(0, IT_SOFT_INT, bit);
         else
-            cpu->clearInterrupt(IT_SOFT_INT, bit);
+            cpu->clearInterrupt(0, IT_SOFT_INT, bit);
     }
 }
 
@@ -88,7 +89,7 @@ getMiscRegName(RegIndex index)
 }
 
 void
-ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
+ISA::setFSReg(int miscReg, RegVal val, ThreadContext *tc)
 {
     BaseCPU *cpu = tc->getCpuPtr();
 
@@ -137,6 +138,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
 
       case MISCREG_PSTATE:
         setMiscRegNoEffect(miscReg, val);
+        break;
 
       case MISCREG_PIL:
         setMiscRegNoEffect(miscReg, val);
@@ -149,9 +151,9 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_HINTP:
         setMiscRegNoEffect(miscReg, val);
         if (hintp)
-            cpu->postInterrupt(IT_HINTP, 0);
+            cpu->postInterrupt(0, IT_HINTP, 0);
         else
-            cpu->clearInterrupt(IT_HINTP, 0);
+            cpu->clearInterrupt(0, IT_HINTP, 0);
         break;
 
       case MISCREG_HTBA:
@@ -163,25 +165,25 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
       case MISCREG_QUEUE_CPU_MONDO_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (cpu_mondo_head != cpu_mondo_tail)
-            cpu->postInterrupt(IT_CPU_MONDO, 0);
+            cpu->postInterrupt(0, IT_CPU_MONDO, 0);
         else
-            cpu->clearInterrupt(IT_CPU_MONDO, 0);
+            cpu->clearInterrupt(0, IT_CPU_MONDO, 0);
         break;
       case MISCREG_QUEUE_DEV_MONDO_HEAD:
       case MISCREG_QUEUE_DEV_MONDO_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (dev_mondo_head != dev_mondo_tail)
-            cpu->postInterrupt(IT_DEV_MONDO, 0);
+            cpu->postInterrupt(0, IT_DEV_MONDO, 0);
         else
-            cpu->clearInterrupt(IT_DEV_MONDO, 0);
+            cpu->clearInterrupt(0, IT_DEV_MONDO, 0);
         break;
       case MISCREG_QUEUE_RES_ERROR_HEAD:
       case MISCREG_QUEUE_RES_ERROR_TAIL:
         setMiscRegNoEffect(miscReg, val);
         if (res_error_head != res_error_tail)
-            cpu->postInterrupt(IT_RES_ERROR, 0);
+            cpu->postInterrupt(0, IT_RES_ERROR, 0);
         else
-            cpu->clearInterrupt(IT_RES_ERROR, 0);
+            cpu->clearInterrupt(0, IT_RES_ERROR, 0);
         break;
       case MISCREG_QUEUE_NRES_ERROR_HEAD:
       case MISCREG_QUEUE_NRES_ERROR_TAIL:
@@ -213,9 +215,9 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
             setMiscRegNoEffect(miscReg, newVal);
             newVal = hpstate;
             if (newVal.tlz && tl == 0 && !newVal.hpriv)
-                cpu->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                cpu->postInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             else
-                cpu->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
+                cpu->clearInterrupt(0, IT_TRAP_LEVEL_ZERO, 0);
             break;
         }
       case MISCREG_HTSTATE:
@@ -241,7 +243,7 @@ ISA::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
     }
 }
 
-MiscReg
+RegVal
 ISA::readFSReg(int miscReg, ThreadContext * tc)
 {
     uint64_t temp;