includes: sort includes again
[gem5.git] / src / arch / sparc / ua2005.cc
index 2389c963d7c061c13c364a4d7883d8e39baef677..d126d5944c499797c878749034ef7f644dede8b7 100644 (file)
@@ -35,6 +35,7 @@
 #include "sim/system.hh"
 
 using namespace SparcISA;
+using namespace std;
 
 
 void
@@ -61,6 +62,26 @@ MiscRegFile::checkSoftInt(ThreadContext *tc)
     }
 }
 
+//These functions map register indices to names
+static inline string
+getMiscRegName(RegIndex index)
+{
+    static string miscRegName[NumMiscRegs] =
+        {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
+         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
+         "stick", "stick_cmpr",
+         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
+         "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
+         "wstate",*/ "gl",
+         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
+         "hstick_cmpr",
+         "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
+         "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
+         "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
+         "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
+         "nresErrorHead", "nresErrorTail", "TlbData" };
+    return miscRegName[index];
+}
 
 void
 MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
@@ -325,8 +346,7 @@ MiscRegFile::processHSTickCompare(ThreadContext *tc)
     // we're actually at the correct cycle or we need to wait a little while
     // more
     int ticks;
-    if ( tc->status() == ThreadContext::Halted ||
-         tc->status() == ThreadContext::Unallocated)
+    if ( tc->status() == ThreadContext::Halted)
        return;
 
     ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -