#include "sim/system.hh"
using namespace SparcISA;
+using namespace std;
void
}
}
+//These functions map register indices to names
+static inline string
+getMiscRegName(RegIndex index)
+{
+ static string miscRegName[NumMiscRegs] =
+ {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
+ "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
+ "stick", "stick_cmpr",
+ "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
+ "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
+ "wstate",*/ "gl",
+ "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
+ "hstick_cmpr",
+ "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
+ "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
+ "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
+ "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
+ "nresErrorHead", "nresErrorTail", "TlbData" };
+ return miscRegName[index];
+}
void
MiscRegFile::setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc)
temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
// Check that the CPU array is fully populated
// (by calling getNumCPus())
- assert(sys->getNumCPUs() > tc->readCpuId());
+ assert(sys->numContexts() > tc->contextId());
- temp |= tc->readCpuId() << STS::shft_id;
+ temp |= tc->contextId() << STS::shft_id;
- for (x = tc->readCpuId() & ~3; x < sys->threadContexts.size(); x++) {
+ for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
switch (sys->threadContexts[x]->status()) {
case ThreadContext::Active:
temp |= STS::st_run << (STS::shft_fsm0 -
// we're actually at the correct cycle or we need to wait a little while
// more
int ticks;
- if ( tc->status() == ThreadContext::Halted ||
- tc->status() == ThreadContext::Unallocated)
+ if ( tc->status() == ThreadContext::Halted)
return;
ticks = ((int64_t)(hstick_cmpr & mask(63)) - (int64_t)stick) -