X86: Define a noop ExtMachInst.

[gem5.git] / src / arch / sparc / utility.hh

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 9a84a82b33da5a352de1f18537296ef2edaab93c..064af9c6ab726e7c60476f59dfbffecef122f60f 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -33,6 +33,7 @@
 
 #include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/misc.hh"
 #include "base/bitfield.hh"
@@ -40,15 +41,13 @@
 
 namespace SparcISA
 {
-
-
     uint64_t getArgument(ThreadContext *tc, int number, bool fp);
 
     static inline bool
     inUserMode(ThreadContext *tc)
     {
-        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
-                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
+        return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
+                 (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
     }
 
     inline bool isCallerSaveIntegerRegister(unsigned int reg) {
@@ -96,7 +95,8 @@ namespace SparcISA
     template <class TC>
     void zeroRegisters(TC *tc);
 
-    inline void initCPU(ThreadContext *tc, int cpuId)
+    inline void
+    initCPU(ThreadContext *tc, int cpuId)
     {
         static Fault por = new PowerOnReset();
         if (cpuId == 0)
@@ -104,7 +104,8 @@ namespace SparcISA
 
     }
 
-    inline void startupCPU(ThreadContext *tc, int cpuId)
+    inline void
+    startupCPU(ThreadContext *tc, int cpuId)
     {
 #if FULL_SYSTEM
         // Other CPUs will get activated by IPIs
@@ -115,6 +116,10 @@ namespace SparcISA
 #endif
     }
 
+    void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+    void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
 } // namespace SparcISA
 
 #endif