Automated merge with ssh://m5sim.org//repo/m5

[gem5.git] / src / arch / sparc / utility.hh

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index f75beb04a3048540b6aae401116f256847678052..9a84a82b33da5a352de1f18537296ef2edaab93c 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -31,14 +31,24 @@
 #ifndef __ARCH_SPARC_UTILITY_HH__
 #define __ARCH_SPARC_UTILITY_HH__
 
+#include "arch/sparc/faults.hh"
 #include "arch/sparc/isa_traits.hh"
+#include "arch/sparc/tlb.hh"
 #include "base/misc.hh"
+#include "base/bitfield.hh"
+#include "cpu/thread_context.hh"
 
 namespace SparcISA
 {
-    inline ExtMachInst
-    makeExtMI(MachInst inst, const Addr &pc) {
-        return ExtMachInst(inst);
+
+
+    uint64_t getArgument(ThreadContext *tc, int number, bool fp);
+
+    static inline bool
+    inUserMode(ThreadContext *tc)
+    {
+        return !(tc->readMiscRegNoEffect(MISCREG_PSTATE & (1 << 2)) ||
+                tc->readMiscRegNoEffect(MISCREG_HPSTATE & (1 << 2)));
     }
 
     inline bool isCallerSaveIntegerRegister(unsigned int reg) {
@@ -81,10 +91,29 @@ namespace SparcISA
 
     /**
      * Function to insure ISA semantics about 0 registers.
-     * @param xc The execution context.
+     * @param tc The thread context.
      */
-    template <class XC>
-    void zeroRegisters(XC *xc);
+    template <class TC>
+    void zeroRegisters(TC *tc);
+
+    inline void initCPU(ThreadContext *tc, int cpuId)
+    {
+        static Fault por = new PowerOnReset();
+        if (cpuId == 0)
+            por->invoke(tc);
+
+    }
+
+    inline void startupCPU(ThreadContext *tc, int cpuId)
+    {
+#if FULL_SYSTEM
+        // Other CPUs will get activated by IPIs
+        if (cpuId == 0)
+            tc->activate(0);
+#else
+        tc->activate(0);
+#endif
+    }
 
 } // namespace SparcISA