arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / utility.hh

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index ee94ef29ac468f580624c633245a59565c9f79f5..ae579969950243c03939a538e15a619f72ae9b09 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -35,10 +35,9 @@
 #include "arch/sparc/registers.hh"
 #include "arch/sparc/tlb.hh"
 #include "base/bitfield.hh"
-#include "base/misc.hh"
+#include "base/logging.hh"
 #include "cpu/static_inst.hh"
 #include "cpu/thread_context.hh"
-#include "sim/fault_fwd.hh"
 #include "sim/full_system.hh"
 
 namespace SparcISA
@@ -58,8 +57,9 @@ uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
 static inline bool
 inUserMode(ThreadContext *tc)
 {
-    return !((tc->readMiscRegNoEffect(MISCREG_PSTATE) & (1 << 2)) ||
-             (tc->readMiscRegNoEffect(MISCREG_HPSTATE) & (1 << 2)));
+    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    return !(pstate.priv || hpstate.hpriv);
 }
 
 /**
@@ -76,7 +76,7 @@ startupCPU(ThreadContext *tc, int cpuId)
 {
     // Other CPUs will get activated by IPIs
     if (cpuId == 0 || !FullSystem)
-        tc->activate(0);
+        tc->activate();
 }
 
 void copyRegs(ThreadContext *src, ThreadContext *dest);
@@ -86,7 +86,7 @@ void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
 void skipFunction(ThreadContext *tc);
 
 inline void
-advancePC(PCState &pc, const StaticInstPtr inst)
+advancePC(PCState &pc, const StaticInstPtr &inst)
 {
     inst->advancePC(pc);
 }