arch-arm: Add initial support for SVE contiguous loads/stores

[gem5.git] / src / arch / sparc / utility.hh

diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index f1c07114827e1f9f2bfa89168342134e40e79200..ae579969950243c03939a538e15a619f72ae9b09 100644 (file)
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -32,59 +32,70 @@
 #define __ARCH_SPARC_UTILITY_HH__
 
 #include "arch/sparc/isa_traits.hh"
-#include "base/misc.hh"
+#include "arch/sparc/registers.hh"
+#include "arch/sparc/tlb.hh"
+#include "base/bitfield.hh"
+#include "base/logging.hh"
+#include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
+#include "sim/full_system.hh"
 
 namespace SparcISA
 {
-    inline ExtMachInst
-    makeExtMI(MachInst inst, const Addr &pc) {
-        return ExtMachInst(inst);
-    }
-
-    inline bool isCallerSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveIntegerRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCallerSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    inline bool isCalleeSaveFloatRegister(unsigned int reg) {
-        panic("register classification not implemented");
-        return false;
-    }
-
-    // Instruction address compression hooks
-    inline Addr realPCToFetchPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    inline Addr fetchPCToRealPC(const Addr &addr)
-    {
-        return addr;
-    }
-
-    // the size of "fetched" instructions (not necessarily the size
-    // of real instructions for PISA)
-    inline size_t fetchInstSize()
-    {
-        return sizeof(MachInst);
-    }
-
-    /**
-     * Function to insure ISA semantics about 0 registers.
-     * @param tc The thread context.
-     */
-    template <class TC>
-    void zeroRegisters(TC *tc);
+
+inline PCState
+buildRetPC(const PCState &curPC, const PCState &callPC)
+{
+    PCState ret = callPC;
+    ret.uEnd();
+    ret.pc(curPC.npc());
+    return ret;
+}
+
+uint64_t getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp);
+
+static inline bool
+inUserMode(ThreadContext *tc)
+{
+    PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
+    HPSTATE hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
+    return !(pstate.priv || hpstate.hpriv);
+}
+
+/**
+ * Function to insure ISA semantics about 0 registers.
+ * @param tc The thread context.
+ */
+template <class TC>
+void zeroRegisters(TC *tc);
+
+void initCPU(ThreadContext *tc, int cpuId);
+
+inline void
+startupCPU(ThreadContext *tc, int cpuId)
+{
+    // Other CPUs will get activated by IPIs
+    if (cpuId == 0 || !FullSystem)
+        tc->activate();
+}
+
+void copyRegs(ThreadContext *src, ThreadContext *dest);
+
+void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
+
+void skipFunction(ThreadContext *tc);
+
+inline void
+advancePC(PCState &pc, const StaticInstPtr &inst)
+{
+    inst->advancePC(pc);
+}
+
+inline uint64_t
+getExecutingAsid(ThreadContext *tc)
+{
+    return tc->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT);
+}
 
 } // namespace SparcISA